SNL310

16-Bit LCD Controller

CLOCK

CS\

RD\

A[0..22]

IN D[0..7]

OUT D[0..7]

62.5ns

(Complete Read Cycle)

4 * n * clocks

CLOCK

CS\

WR\

A[0..22]

IN D[0..7]

OUT D[0..7]

62.5ns

(Complete Write Cycle)

4 * n * clocks

Access timing for 16-bit mode

Figure-10

Figure-9 and Figure-10 show the accessing timing for 8-bit mode and 16-bit mode.

Considering to compatible with different access time memory, user can set different

speed ratio in the special register “EDI” (External Device Information register). The

value “n” in Figure-9 and Figure-10 is relative to the setting of speed ratio of EDI

register.

Ver: 1.7

May 2, 2003

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