VSP01M02 datasheet(21/91 Pages) TI1

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Mode Confusion

10-Bit

Address

(6-BitRegisterArea)

22-BitData

SDATA

10-Bit

Address

(AddA)

D21

6-Bit Data

(Storeto

AddA)

6-Bit Data

(Storeto

AddA+1)

6-Bit Data

(Storeto

AddA+2)

Ignored

SPIRecognition

Read and Write Batting

VSP01M01

VSP01M02

www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009

If 22 bits of data are sent to a 6-bit register area, the SPI recognizes continuous write mode, because usually

only 6-bit data should be sent to 6-bit register area in standard write mode, as shown in Figure 15. The

end-of-data point is recognized by the rising edge of CS.

Figure 15. Mode Confusion

SPI recognition is shown in Table 9.

Table 9. SPI Recognition

DATA WIDTH

ADDRESS AREA

6-BIT

16-BIT

22-BIT

32-BIT

6-bit register

Standard(1) (one word)

Continuous(2) (two words)

Continuous (three words)

Continuous (five words)

16-bit memory

Ignored

Standard (one word)

Standard(3) (one word)

Continuous (two words)

22-bit memory

Ignored

Standard (one word)

(1)

Shaded cells indicate standard operation.

(2)

Continuous = continuous write mode.

(3)

Standard = standard write mode.

Address 100h-3FFh is the memory area. HA, VA, and HS access this memory area to read programs. If the SPI

writes to the memory area during a program read, the programmed operation is cancelled. SPI operation should

be done with TG disable. If SPI operation must be done with TG enable (TG operating), the SPI must write for a

no-read term (no toggling term). For the register area (000h-0FFh), this precaution is not necessary.

The update timing of each register is specified in Table 10.

Table 10. Updated Timing

UPDATE TIMING

000h

Real time

001h-01Fh

Timing specified at bits 0-2 of 000h (AFE update)

020h-035h

Real time

036h[2:0]

VD; refer to the CCD Timing Composition section of the TG (Timing Generator) Section for details.

036h[5:3]

TRIG; refer to the CCD Timing Composition section of the TG (Timing Generator) Section for details.

037h-0FFh

Timing specified at bit 3 of 000h (TG update)

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