1

FEATURES

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1CLR

1D

1CLK

1PRE

1Q

1Q

GND

2CLR

2D

2CLK

2PRE

2Q

2Q

D OR PW PACKAGE

(TOP VIEW)

DESCRIPTION/ORDERING INFORMATION

SN74LVC74A-EP

DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP

WITH CLEAR AND PRESET

SCAS751C – DECEMBER 2003 – REVISED SEPTEMBER 2007

www.ti.com

• Controlled Baseline

• Inputs Accept Voltages to 5.5 V

–

One Assembly/Test Site, One Fabrication

• Max t

Site

• Typical V

• Extended Temperature Performance of –40°C

to 125

°C and –55°C to 125°C

• Typical V

• Enhanced Diminishing Manufacturing Sources

(DMS) Support

• Enhanced Product-Change Notification

• Operates From 2 V to 3.6 V

(1)

Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,

data at the D input can be changed without affecting the levels at the outputs.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as a translator in

a mixed 3.3 V/5 V system environment.

ORDERABLE PART NUMBER

TOP-SIDE MARKING

SOIC – D

Reel of 2500

SN74LVC74AQDREP

LVC74AE

–40

°C to 125°C

TSSOP – PW

Reel of 2000

SN74LVC74AQPWREP

LVC74AE

SOIC – D

Reel of 2500

SN74LVC74AMDREP

LVC74AM

–55

°C to 125°C

TSSOP – PW

Reel of 2000

SN74LVC74AMPWREP

LVC74AM

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2)

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2003–2007, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.