TNETE2008

OctalPHY

EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS042B – DECEMBER 1997 – REVISED JUNE 1998

13

POST OFFICE BOX 655303

LED control signals

LACTVE, LLINK, and LDUPCOL

Outputs are each capable of sourcing and sinking up to 40 mA; active

low for even, active high for odd-numbered channels.

LSEL0–LSEL7

Outputs each source/sink 10 mA; active low for odd, active high for

even-numbered channels.

When RESET is active (low), all LEDs are illuminated during their time slot as a lamp test feature, regardless

of the state of the corresponding status signal. CLK input must be driven with a valid clock for this to occur.

JTAG test access port

Compliant with IEEE Std 1149.1, the TAP is composed of five terminals. These terminals interface serially with

the device and the board on which it is installed for boundary-scan testing. The TNETE2008 implements the

following JTAG instructions:

INSTRUCTION

TYPE

NAME

JTAG

OPCODE

ACTION

Mandatory

EXTEST

0000

External boundary-scan test

Mandatory

SAMPLE/PRELOAD

0001

Initialization for boundary-scan test

Optional

IDCODE

0100

Scans out TNETE2008 identification code

Optional

HIGHZ

0011

Sets all digital output pins on TNETE2008 to high impedance

Mandatory

BYPASS

1111

Connects 1-bit bypass register between TDI and TDO

The IDCODE for the TNETE2008 is:

CODE

VARIANT

PART NUMBER

MANUFACTURER

LEAST

SIGNIFICANT

BYTE

Binary

0000b

0000000001010000

000 0001 0111b

1b

The JTAG terminals do not have internal pullup resistors, so, to comply fully with IEEE Std 1149.11, external

resistors must be connected to JTMS, JTCLK, JTDI, and JTRST. All other JTAG opcodes are reserved for

manufacturing test and should not be used.

global reset logic

At initial power up, the TNETE2008 performs an internal reset. No external reset circuitry is required. However,

operation of the TNETE2008 is not specified for 50 ms after power up.

During operation, a full reset of the device can be performed by taking RESET low for not less than 50

µs.

Operation of the device is not ensured for 5 ms after reset ends.

The device resets itself if CLK is lost for any reason. CLK loss is detected in 200

µs.

Data is not valid on the multiplexed MAC interface until normal operation resumes, after any reset, and then

after two complete IFSYNC cycles have passed.

All signals in the multiplexed MAC interface are driven to 0 during reset, except for IFSYNC, which is driven to 1

during reset.