Introduction

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1

Introduction

The TPS75005EVM-023 helps design engineers evaluate the operation and performance of the

TPS75005 for possible use in their own circuit applications. The TPS75005 is optimized to be a complete

power management solution for Texas Instruments

’ C2000™ real-time microcontrollers and other

DSP/FPGA/ASIC MCUs. The device contains dual, 500-mA LDOs. Each LDO output is monitored by an

internal supervisor (SVS) circuit to determine the Power Good (PG) signal. A third supervisor allows the

customer to independently monitor an additional external voltage. On this EVM, the third SVS monitor is

preset by a resistor divider to monitor an external 2.5-V power rail. The two power outputs are enabled

and disabled by a single EN logic input. Sequence and soft-start circuitry provide a means to program the

start-up characteristics and to ensure well-behaved output ramp-up.

This document describes the configuration and setup of the TPS75005EVM-023 board.

2

Setup

This section describes the jumpers and connectors on the EVM as well as how to properly connect, set

up, and use the TPS75005EVM-023.

2.1

Input / Output Connector Descriptions

J1: EXT SVS

This connector is the input to the voltage monitoring function (VMON) of the TPS75005. When the

voltage at this header drops below approximately 2.35 V, the VDET output drops to logic low. The

VDET output can be measured at TP1.

J2: VIN

This connector is the input power-supply voltage connector. The positive input lead and ground return

lead from the input power supply should be twisted and kept as short as possible to minimize

electromagnetic interference (EMI) transmission.

J3: GND

This connector is the return connection for the input power supply. The positive input lead and ground

return lead from the input power supply should be twisted and kept as short as possible to minimize

EMI.

J4: VOUT2

This connector is the positive output of LDO-2. The LDO-2 output is regulated to 3.3 V.

J5: GND

This connector is the return connection for LDO-2.

J6: VOUT1

This connector is the positive output of LDO-1. The LDO-1 output is regulated to 1.9 V if jumper JP2 is

installed, and 1.8 V if jumper JP2 is not installed.

J7: GND

This connector is the return connection for LDO-1.

2

TPS75005EVM-023

SBVU019A

– October 2011 – Revised October 2011

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