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SN74LVC06AMDREP 数据表(PDF) 2 Page - Texas Instruments

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部件名 SN74LVC06AMDREP
功能描述  HEX INVERTER BUFFER/DRIVER WITH OPEN DRAIN OUTPUTS
PDF  9 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

SN74LVC06AMDREP 数据表(HTML) 2 Page - Texas Instruments

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A
Y
Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
SN74LVC06A-EP
HEX INVERTER BUFFER/DRIVER
WITH OPEN DRAIN OUTPUTS
SCAS832A – APRIL 2007 – REVISED MAY 2007
LOGIC DIAGRAM, EACH INVERTER (POSITIVE LOGIC)
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–55
°C to 125°C
SOIC – D
Reel of 2500
SN74LVC06AMDREP
LVC06AM
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range(2)
–0.5
6.5
V
VO
Output voltage range
–0.5
6.5
V
IIK
Input clamp current
VI < 0 V
–50
mA
IOK
Output clamp current
VO < 0 V
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
θ
JA
Package thermal impedance(3)
86
°C/W
Tstg
Storage temperature range
–65
150
°C
Ptot
Power dissipation(4)
TA = –55°C to 125°C
500
mW
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The package thermal impedance is calculated in accordance with JESD 51-7.
(4)
Above 70
°C the value of P
tot derates linearly with 8 mW/K.
TA = 25°C
–55
°C to 125°C
UNIT
MIN
MAX
MIN
MAX
Operating
1.65
3.6
1.65
3.6
VCC
Supply voltage
V
Data retention only
1.5
1.5
VCC = 1.65 V to 1.95 V
0.65
× V
CC
0.65
× V
CC
High-level
VIH
VCC = 2.3 V to 2.7 V
1.7
1.7
V
input voltage
VCC = 2.7 V to 3.6 V
2
2
VCC = 1.65 V to 1.95 V
0.35
× V
CC
0.35
× V
CC
Low-level
VIL
VCC = 2.3 V to 2.7 V
0.7
0.7
V
input voltage
VCC = 2.7 V to 3.6 V
0.8
0.8
VI
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
0
5.5
0
5.5
V
(1)
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
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