ThunderLAN

™ TNETE110

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS018B – MARCH 1995 - REVISED MAY 1996

8

POST OFFICE BOX 1443

Pin Functions (Continued)

PIN

TYPE†

DESCRIPTION

NAME

NO.

TYPE†

DESCRIPTION

FXMTP

FXMTN

97

98

A

10 Base-T transmit pair. FXMTP and FXMTN are differential line transmitter outputs.

RESERVED

120

I

Reserved. Tie this pin low.

FRCVN

FRCVP

105

103

A

10 Base-T receive pair. FRCVN and FRCVP are differential line receiver inputs and connect to the

receive pair through transformer isolation, etc.

FXTL1

FXTL2

113

114

A

Crystal oscillator pins. Drive FXTL1 and FXTL2 from a 20-MHz crystal oscillator module

POWER

VDDI

6, 14,

34, 48,

122,

136,

142

PWR

PCI VDD pins. VDDI pins provide power for the PCI I/O pin drivers. Connect VDDI pins to a 5-V power

supply when using 5-V signals on the PCI bus. Connect VDDI pins to a 3-V power supply when using

3-V signals on the PCI bus

VDDL

22, 37,

58, 70

79, 84

94, 130

PWR

Logic VDD pins (5 V). VDDL pins provide power for internal TNETE110 logic and they always should

be connected to 5-V power supply.

VDDOSC

115

PWR

Analog power pin. VDDOSC is the 5-V power for the crystal oscillator circuit.

VDDR

104

107

PWR

Analog power pin. VDDR is the 5-V power for the receiver circuitry.

VDDT

96

PWR

Analog power pin. VDDT is the 5-V power for the transmitter circuitry.

VDDVCO

117

PWR

Analog power pin. VDDVCO is the 5-V power for the voltage controller oscillator (VCO) and filter input.

VSSI

3, 10,

26, 31,

40, 52,

67, 88,

127,

139

PWR

PCI I / O ground pins

VSSL

18, 44,

63, 75,

92, 133

PWR

Logic ground pins

VSSOSC

112

PWR

Analog power pin. Ground for crystal oscillator circuit

VSSR

102

110

PWR

Analog power pin. Ground for receiver circuitry

VSST

101

PWR

Analog power pin. Ground for transmitter circuitry

VSSVCO

119

PWR

Analog power pin. Ground for VCO and filter input

† I = input, A = analog, PWR = power

architecture

The major blocks of the TNETE110 include the PCI interface (PCIIF), the protocol handler (PH), the physical

layer (PHY), the FIFO pointer registers (FPREGS), the FIFO SRAM (FSRAM), and a test-access port (TAP).

The functionality of these blocks is described in the following sections.

PCI interface (PCIIF)

The TNETE110 PCIIF contains a byte-aligning DMA controller that allows frames to be fragmented into any byte

length and transferred to any byte address while supporting 32-bit data streaming. For multipriority networks,

it can provide multiple data channels, each with separate lists, commands, and status. Data for the channels

is passed to and from the PH by way of circular buffer FIFOs in the SRAM, which are controlled through FIFO