SN74LVC2G00WDCTREP datasheet(1/9 Pages) TI1

部件名	SN74LVC2G00WDCTREP

功能描述	DUAL 2-INPUT POSITIVE-NAND GATE

PDF	9 Pages

Scroll/Zoom	100%

制造商	TI1 [Texas Instruments]

网页	http://www.ti.com

标志

1 / 9 page

www.ti.com

FEATURES

DCT PACKAGE

(TOP VIEW)

1

2

3

4

8

7

6

5

1A

1B

2Y

GND

VCC

1Y

2B

2A

DESCRIPTION/ORDERING INFORMATION

SN74LVC2G00W-EP

DUAL 2-INPUT POSITIVE-NAND GATE

SCES645 – SEPTEMBER 2005

•

Controlled Baseline

•

±24-mA Output Drive at 3.3 V

– One Assembly/Test Site, One Fabrication

•

Typical VOLP (Output Ground Bounce)

Site

<0.8 V at VCC = 3.3 V, TA = 25°C

•

Extended Temperature Performance of –55

°C

•

Typical VOHV (Output VOH Undershoot)

to 115

°C

>2 V at VCC = 3.3 V, TA = 25°C

•

Enhanced Diminishing Manufacturing

•

Ioff Supports Partial-Power-Down Mode

Sources (DMS) Support

Operation

•

Enhanced Product-Change Notification

•

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

Qualification Pedigree (1)

•

ESD Protection Exceeds JESD 22

•

Supports 5-V V

CC Operation

– 2000-V Human-Body Model (A114-A)

•

Inputs Accept Voltages to 5.5 V

– 1000-V Charged-Device Model (C101)

•

Max t

pd of 5.3 ns at 3.3 V

•

Low Power Consumption, 10-

µA Max I

CC

(1)

Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

This dual 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G00W-EP performs the Boolean function Y = A

• B or Y = A + B in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

TA

PACKAGE(1)

ORDERABLE PART NUMBER

TOP-SIDE MARKING(2)

–55

°C to 115°C

SSOP – DCT

Reel of 3000

SN74LVC2G00WDCTREP

C00_ _ _

(1)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2)

DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

类似零件编号 - SN74LVC2G00WDCTREP

制造商	部件名	数据表	功能描述
Texas Instruments	SN74LVC2G00	343Kb / 13P	DUAL 2 INPUT POSITIVE NAND GATE
	SN74LVC2G00	527Kb / 13P	DUAL 2-INPUT POSITIVE-NAND GATE
	SN74LVC2G00	1,001Kb / 24P	Dual 2-Input Positive-NAND Gate
	SN74LVC2G00	714Kb / 26P	SN74LVC2G00 Dual 2-Input Positive-NAND Gate REVISED JANUARY 2015
	SN74LVC2G00DCT3	1,001Kb / 24P	Dual 2-Input Positive-NAND Gate

More results

类似说明 - SN74LVC2G00WDCTREP

制造商	部件名	数据表	功能描述
Texas Instruments	SN74LVC2G00	343Kb / 13P	DUAL 2 INPUT POSITIVE NAND GATE
	SN74AUC2G00	259Kb / 11P	DUAL 2-INPUT POSITIVE-NAND GATE
	SN74ALS8003A	69Kb / 4P	DUAL 2-INPUT POSITIVE-NAND GATE
	SN74AS8003	293Kb / 8P	DUAL 2-INPUT POSITIVE-NAND GATE
	SN74AUC2G00	517Kb / 13P	DUAL 2-INPUT POSITIVE-NAND GATE
	SN74LVC2G00	527Kb / 13P	DUAL 2-INPUT POSITIVE-NAND GATE
Unisonic Technologies	U74LVC2G00	161Kb / 6P	DUAL 2-INPUT POSITIVE-NAND GATE
Texas Instruments	SN74AHC2G00	75Kb / 5P	DUAL 2-INPUT POSITIVE-NAND GATE
	SN74ALS8003A	92Kb / 5P	DUAL 2-INPUT POSITIVE-NAND GATE
	SN74LVC2G00	1,001Kb / 24P	Dual 2-Input Positive-NAND Gate