TNETE211

ThunderLAN

™ TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR

100VG-AnyLAN

SPWS019 – MAY 1995

4

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Pin Functions

Following is a list of TNETE211 physical media independent (PMI) pins and their functions. Assignment of pin

numbers follows the order necessary to allow ThunderLAN and IEEE 802.12-compliant PMD devices to be laid

out without any traces crossing. Pin names use the convention of indicating active low signals with an overbar.

All ThunderLAN signals begin with an M (for MII). All manufacturing test signals begin with a T (for Test). All

network interface signals begin with a P (for Physical Media Dependent).

PIN

TYPE†

DESCRIPTION

NAME

NO.

TYPE†

DESCRIPTION

PHYSICAL MEDIA INDEPENDENT INTERFACE PINS (DEMAND-PRIORITY MODE)

MRST

1

I

MII reset. MRST resets signal to the PMD front end (active low).

MDIO

3

I/O

Management data I / O. MDIO is the serial management interface to PMD chip.

MDCLK

5

I

Management data clock. MDCLK is the serial management interface to PMD chip.

MRXER

7

O

Receive error. MRXER indicates reception of a coding error on received data.

MRXDV

8

O

Receive data valid. MRXDV indicates data on MRXD[0–3] is valid.

MRXD3

MRXD2

MRXD1

MRXD0

9

10

11

12

O

Receive data. MRXD[0–3] represents the nibble receive data from the PMD front end. The PMI

indicates the priority of the incoming frames on these pins on the cycle before the assertion of MRXDV

(the cycle before frame reception begins). MRXD1 indicates the transmission priority of the received

frame. A value of zero indicates normal transmission, a value of one indicates priority transmission.

Data on these pins is always synchronous to MRCLK.

MRCLK

14

O

Receive clock. MRCLK is the receive clock source from the PMI front end.

MCRS

16

O

Carrier sense. MCRS is not used in VG operation, but is connected to the TNETE100 MII for

completeness.

MCOL

17

O

Collision sense. MCOL indicates that the PMI is transmitting on the physical media.

• MCOL (active low) is used to acknowledge a transmission request. TNETE100 must begin

frame transmission 50 MTCLK cycles after the assertion (low) of MCOL.

MCOL is held asserted low until the PMI has completed all transmission tasks.

MTXER

19

I

Transmit error. MTXER allows coding errors to be propagated across the MII.

MTXEN

20

I

Transmit enable. MTXEN indicates valid transmit data on MTXD[0 – 3].

MTXD3

MTXD2

MTXD1

MTXD0

21

22

23

24

I

Transmit data. MTXD[0–3] represents the nibble transmit data from TNETE100; when MTXEN is

asserted, these pins carry data transmissions. When MTXEN is not asserted (frame transmission not

in progress), these pins carry control information.

• MTXD0 asserted (high) indicates TNETE100 is requesting frame transmission.

• MTXD1 indicates the transmission priority required. A value of zero indicates normal

transmission; a value of one indicates priority transmission.

Data/control on these pins is always synchronous to MTCLK.

MTCLK

26

O

Transmit clock. MTCLK is the transmit clock source from the PMI front end. Used to clock transmit and

control data into the PMI device.

† I = input, O = output, and I / O = 3-state input / output