TNETE211

ThunderLAN

™ TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR

100VG-AnyLAN

SPWS019 – MAY 1995

5

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Pin Functions (Continued)

PIN

TYPE†

DESCRIPTION

NAME

NO.

TYPE†

DESCRIPTION

CONFIGURATION PINS (WIRE TYPE)

CONFIG0

CONFIG1

CONFIG2

CONFIG3

28

29

30

31

I

Configuration. CONFIG[0–3] indicate the current wire configuration of the PMI.

PHYSICAL MEDIA DEPENDENT (PMD) PINS (PINS CONNECTING TO THE IEEE 802.12-COMPLIANT PMD DEVICE)

PMRST

33

O

PMD reset/detect. PMRST, when seen low, resets the PMD.

PTLS0

PTLS1

PTLS2

35

36

37

O

Transmit line status. The PTLS[0–2] pins are used to set the current transmit line state.

PRLS0

PRLS1

PRLS2

PRLS3

39

40

41

42

I

Receive line state. The PRLS[0–3] pins are used to determine the current receive-line state from the

PMD.

PRLSDIR

44

I

PMD RLS direct. When the PRLSDIR pin is asserted high, this pin allows the TNETE211 PMD pins

to directly connect to the IEEE 802.12 MII interface. When low, this pin allows the TNETE211 PMD pins

to directly connect to the AT&T ATT2X01.

PRXCLK

46

I

Receive data clock. PRXCLK is the receive data clock reference.

PRXD0

PRXD1

PRXD2

PRXD3

48

49

50

51

I

Receive data. PRXD[0–3] are used to transfer the data streams received from the PMD.

PTXD0

PTXD1

PTXD2

PTXD3

53

54

55

56

O

Transmit data. PTXD0[0–3] transmit data to the PMD device.

POSCEN

58

O

Oscillator enable. POSCEN is used to enable the TNET211 30-MHz oscillator. When POSCEN is high,

the oscillator is driven to the TNETE211. When POSCEN is low, the oscillator is disabled. The

POSCEN is mainly used for power-down functions.

PTXEN

60

O

Transmit enable. PTXEN indicates valid data on the PTXD[0–3] pins.

PRXEN

61

O

Receive enable. PRXEN causes the PMD to drive the received data to the PRXD[0–3] pins.

PTLSWEN

62

O

Transmit line state write enable. PTLSWEN indicates when the PTLS[0–2] pins are valid.

PRLSREN

63

O

Receive line state read enable. PRLSREN indicates when the PRLS[0–3] pins are valid.

CLK

65

I

Main clock. CLK is the 30-MHz clock pin used to drive all internal transmit and line state control

functions.

DEVSEL0

DEVSEL1

DEVSEL2

DEVSEL3

DEVSEL4

67

68

69

70

71

I

Device select. DEVSEL[0–4] are used for PMI device selection. The device number in the MII is

compared with these pins for the MII read-and-write operations.

† I = input, O = output, I / O = 3-state input / output