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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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SC4530 数据表(PDF) 17 Page - Semtech Corporation |
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SC4530 数据表(HTML) 17 Page - Semtech Corporation |
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17 / 23 page  7 SC4530 U1 VOUT L1 VIN C3 R4 R1 C4 R5 C2 R2 C5 C1 GND SW Figure 12. Suggested PCB Layout for the SC4530 Shortening the traces at the SW and BST nodes reduces the parasitic trace inductance at these nodes.This not only reduces EMI, but also decreases switching voltage spikes at these nodes. Shielding the FB trace from the SW and the BST nodes with ground traces is a good precaution in mitigating switching transient disturbance. Figure 2 shows an example of external component placement around the SC4530. The exposed pad should be soldered to a large power ground plane as the ground copper acts as a heat sink for the device. Applications Information (Continued) |
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