BL7430EC 104-bit EEPROM Smart

Counter Circuit

http://www.belling.com.cn

- 3 -

8/16/2006

Total 4 Pages

Writing operation

When RST=1 and CLK=0, we set R mark, under this condition if next clock pulse comes the

address-counter will not increase and go into writing operation during the clock high level. The

address-counter is re-effective and writing is finished at the clock falling edge. During the issue

mode, R mark is useless to the cells of manufacturer code area; during the user mode, R mark

is useless to the cells of code area for both manufacturer and issuer.

Add

n

n+1

n+2

IO

CLK

RST

t

d5

n

n+1

n+1

t

d6

t

d7

t

s

t

HW

Write Address

Erasing operation

Erasing operation to any stage will lead to the automatic erasing of next lower stage.

Add

n

n+1

IO

CLK

RST

t

S

t

HW

n

n

t

d6

n

t

HE

t

S

t

d7

Erasing 8 Bits with Carry

Power on and reset

The address is reset after power on. RST keep”1” and must last longer than one clock cycle.

When RST is changed to low level, the content in the “0” address is shown on I/O port. The

About Comparison of Transmission Password

Password comparison must be executed immediately after write “0” operation

RST

CLK

ADDRESS

I/O

D8

1

D8

2

D103

D8

0

D0

0

1

104

81

82

80

103

td8

td9

td10

EC bit addr

Bit output Write one bit EC

EC(LSB-1)

~EC(MSB-1)

tHW

• Package

Module package, the module type according to customer demand.