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CXD3003 数据表(PDF) 49 Page - Sony Corporation |
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CXD3003 数据表(HTML) 49 Page - Sony Corporation |
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49 / 137 page  – 49 – CXD3003R $DX commands See "$CX commands". Command bit DCLV PWM MD = 1 DCLV PWM MD = 0 Digital CLV PWM mode specified. Both MDS and MDP are used. CLV-W and CAV-W modes cannot be used. Digital CLV PWM mode specified. Ternary MDP values are output. CLV-W and CAV-W modes can be used. Description Command bit TB = 0 TB = 1 TP = 0 TP = 1 Bottom hold at a cycle of RFCK/32 in CLVS and CLVH modes. Bottom hold at a cycle of RFCK/16 in CLVS and CLVH modes. Peak hold at a cycle of RFCK/4 in CLVS mode. Peak hold at a cycle of RFCK/2 in CLVS mode. Description Command Data 1 CLV CTRL DCLV PWM MD TB TP Gain CLVS D23 D22 D21 D20 Command bit FCSW PCC1 PCC0 Processing The VPCO1 signal is output and the VPCO2 pin is high impedance. The VPCO1 and 2 pin outputs are high impedance. The VPCO1 pin output is low and the VPCO2 pin is high impedance. The VPCO1 pin output is high and the VPCO2 pin is high impedance. The VPCO1 and 2 signals are output. The VPCO1 and 2 pin outputs are high impedance. The VPCO1 and 2 pin outputs are low. The VPCO1 and 2 pin outputs are high. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 • Processing for the $CX commands PCC1 and PCC2 and the $EX command FCSW is shown below. |
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