STULPI01B_12 datasheet(37/44 Pages) STMICROELECTRONICS

37 / 44 page

STULPI01A, STULPI01B

ULPI registers

Doc ID 14817 Rev 4

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Note:

Address 14h(Read-only with auto-clear).

These bits are set by the STULPI01 when an unmasked change occurs on the

corresponding internal signal. The STULPI01 automatically clears all bits when the link

reads this register, or when Low-power mode is entered. The STULPI01 also clears this

ClockSuspendM. The interrupt circuitry is powered down in any mode when both rising and

falling edge enables are disabled. To ensure the interrupts are detectable when the clock is

powered down, the link should enable both rising and falling edges.

The STULPI01 follows the rules in Table 20 for setting any latch register bit. It is important to

note that if the register read data is returned to the link in the same cycle that a USB

interrupt latch bit is to be set, the interrupt condition is given immediately in the register read

data and the latch bit is not set.

Note that it is optional for the link to read the USB interrupt latch register in Synchronous

mode because the RX CMD byte already indicates the interrupt source directly.

Table 23.

USB interrupt latch register

Field name

Bits

Access

Reset

Description

Host disconnect

latch

0rd