L5962

Doc ID 16819 Rev 2

19/24

6

Data transmission from microprocessor to the L5962 and viceversa takes place through the

positive supply voltage must be connected).

6.1

Data validity

As shown by Figure 5, the data on the SDA line must be stable during the high period of the

clock. The HIGH and LOW state of the data line can only change when the clock signal on

the SCL line is LOW.

6.2

Start and stop conditions

As shown by Figure 6 a start condition is a HIGH to LOW transition of the SDA line while

SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is

HIGH.

6.3

Byte format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an

acknowledge bit. The MSB is transferred first.

6.4

Acknowledge

The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock

pulse (see Figure 6). The receiver** the acknowledges has to pull-down (LOW) the SDA line

during the acknowledge clock pulse, so that the SDAline is stable LOW during this clock

pulse.

* Transmitter

–

master (µP) when it writes an address to the L5962

–

slave (L5962) when the µP reads a data byte from L5962

** Receiver

–

slave (L5962) when the µP writes an address to the L5962

–

master (µP) when it reads a data byte from L5962

Figure 5.

SDA

SCL

DATA LINE

STABLE, DATA

VALID

CHANGE

DATA

ALLOWED

D99AU1031