STA540SAN

General structure

Doc ID 18306 Rev 1

23/26

8.9

PCB-layout grounding (general rules)

The device has two distinct ground leads, P_GND (power ground) and S_GND (signal

ground) which are practically disconnected from each other at chip level. Correct operation

requires that P_GND and S_GND leads be connected together on the PCB layout by means

of reasonably low-resistance tracks.

For the PCB ground configuration a star-like arrangement, where the center is represented

by the supply-filtering electrolytic capacitor ground, is recommended. In such context, at

least two separate paths must be provided; one for power ground and one for signal ground.

The correct ground assignments are as follows:

standby capacitor (pin 7, or any other standby driving networks): on signal ground

SVR capacitor (pin 6): on signal ground and to be placed as close as possible to the

device

input signal ground (from active/passive signal processor stages): on signal ground

supply filtering capacitors (pins 3 and 13): on power ground. The negative terminal of

the electrolytic capacitor must be directly tied to the battery negative line and this

should represent the starting point for all the ground paths.

8.10

Mute function

If the mute function is required, it can be accessed on SVR (pin 6) as shown in Figure 34.

Figure 34.

Components for layout

Using a different value for R1 than the suggested 3.3 k

Ω, results in two different situations:

R1 > 3.3 k

Ω:

–

Pop noise improved

–

Lower mute attenuation

R1 < 3.3 k

Ω:

–

Pop noise degradation

–

Higher mute attenuation

0.22

µF

1

DIAGNOSTICS

4

7

D06AU1632_bc

10

µF

10K

ST-BY

IN L

0.47

µF

5

IN BRIDGE

12

470

µF

6

13

1000

µF

100nF

3

VS

2

15

14

OUT L

8

9

10

OUT

BRIDGE

11

0.22

µF

IN R

OUT R

2200

µF

2200

µF

R1 3.3K

R2 10K

MUTE

5V

0

PLAY