TDA7512F datasheet(20/45 Pages) STMICROELECTRONICS

20 / 45 page

Functional description

TDA7512F

20/45

Doc ID 12668 Rev 2

4.5.5

Inlock detector

Switching the chargepump in low current mode can be done either via software or

automatically by the inlock detector, by setting bit LDENA to "1".

After reaching a phase difference about lower than 40nsec the chargepump is forced in low

current mode. A new PLL divider alternation by I2C-Bus will switch the chargepump in the

high current mode.

4.5.6

Low noise CMOS op-amp

An internal voltage divider at pin VREF2 connects the positive input of the low noise op-

amp. The charge pump output connects the negative input. This internal amplifier in

cooperation with external components can provide an active filter.

While the high current mode is activated LPHC output is switched on.

4.5.7

IF counter block

The aim of IF counter is to measure the intermediate frequency of the tuner. The input signal

is the 10.7MHz IF level after limiter.

The grade of integration is adjustable by eight different measuring cycle times. The

tolerance of the accepted count value is adjustable, to reach an optimum compromise for

search speed and precision of the evaluation.

4.5.8

Sampling timer

A sampling timer generates the gate signal for the main counter. The basically sampling

time are in FM mode 6.25kHz (tTIM=160μs).

This is followed by an asynchronous divider to generate several sampling times.

4.5.9

Intermediate frequency main counter

This counter is a 11 - 21-bit synchronous autoreload down counter. Five bits (CF) are

programmable to have the possibility for an adjust to the centre frequency of the IF-filter.

The counter length is automatic adjusted to the chosen sampling time.

At the start the counter will be loaded with a defined value which is an equivalent to the

divider value (tSample xfIF).

If a correct frequency is applied to the IF counter frequency input at the end of the sampling

time the main counter is changing its state from 0h to 1FFFFFh.

This is detected by a control logic and an external search stop output is changing from LOW

to HIGH. The frequency range inside which a successful count result is adjustable by the

EW bits.

Counter result succeeded:

tTIM ≥ tCNT - tERR

tTIM ≤ tCNT + tERR

Counter result failed:

tTIM > tCNT + tERR

CNT

1696

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