STLC3055N

Functional description

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Figure 6.

Metering pulse generation circuit.

The waveform so generated is then filtered and injected on the line.

The low pass filter can be obtained using the integrated buffer OP1 connected between pin

FTTX (OP1 non inverting input) and RTTX (OP1 output) (see Figure 6) and implementing a

"Sallen and Key" configuration. Depending on the external components count it is possible

to build an optimised application depending on the distortion level required. In particular

harmonic distortion levels equal to 13 %, 6 % and 3 % can be obtained respectively with

first, second and third order filters (see Figure 6).

The circuit showed in Figure 8: Application diagram with metering pulse generation. on

page 20 is related to the simple first order filter.

Once the shaped and filtered signal is obtained at RTTX buffer output it is injected on the

TIP/RING pins with a +6 dB gain or +12 dB gain.

It should be noted that this is the nominal condition obtained in presence of ideal TTX echo

cancellation (obtained via proper setting of RTTX and CTTX).

In addition, the effective level obtained on the line will depend on the line impedance and the

protection resistors value. In the typical application (TTX line impedance =200

Ω, RP = 50 Ω,

and ideal TTX echo cancellation) the metering pulse level on the line will be 1.33 or 2.66

times the level applied to the RTTX pin.

As already mentioned the metering pulse echo cancellation is obtained by means of two

external components (RTTX and CTTX) that should match the line impedance at the TTX

frequency. This simple network has a double effect:

●

Synthesize a low output impedance at the TIP/RING pins at the TTX frequency.

●

Cut the eventual TTX echo that will be transferred from the line to the TX output.

4.2.4

Ringing

When this mode is selected STLC3055N self generate an higher negative battery (-70 V

typ.) in order to allow a balanced ringing signal of typically 65 Vpeak.

In this condition both the DC and AC feedback are disabled and the SLIC line drivers

operate as voltage buffers. The ring waveform is obtained toggling the D2 control bit at the

CTTX1

CTTX2

CS

RLV

RLV

SQTTX

BURST

D0

CKTTX

SHAPING

GENERATOR

Square wave pulse metering

Sinusoidal wave

pulse metering

RTTX

FTTX

Low Pass Filter

-

+

OP1

CFL

R1

R2

C2

C1

Required external components vs. filter order.

Order

CFL

R1

C1

R2

C2

THD

1

X13%

2

XXX

X

6%

3

X

XXX

X

3%