34

Am29F032B

21610D8 November 11, 2009

D A TA

SH EE T

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

programming typicals assume checkerboard pattern.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does

the device set DQ5 = 1. See the section on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 5 for further

information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTIC

TSOP AND SO PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

DATA RETENTION

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

Sector Erase Time

1

8

sec

Excludes 00h programming prior to

erasure (Note 4)

Chip Erase Time

64

sec

Byte Programming Time

7

300

µs

Excludes system-level overhead

(Note 5)

Chip Programming Time (Note 3)

28.8

86.4

sec

Description

Min

Max

–1.0 V

–100 mA

+100 mA

Parameter

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

Input Capacitance

6

7.5

pF

Output Capacitance

8.5

12

pF

Control Pin Capacitance

7.5

9

pF

Parameter

Test Conditions

Min

Unit

Minimum Pattern Data Retention Time

150

° C10

Years

125

° C20

Years