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CXP87452 数据表(PDF) 21 Page - Sony Corporation |
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CXP87452 数据表(HTML) 21 Page - Sony Corporation |
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21 / 32 page ![]() – 21 – CXP87452/87460 Serial transfer (CH1) (SIO mode) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Symbol Pin Min. Max. Unit Condition SCK1 cycle time SCK1 high and low level widths SI1 input setup time (against SCK1 ↑) SI1 input hold time (against SCK1 ↑) SCK1 ↓→ SO1 delay time tKCY tKH tKL tSIK tKSI tKSO SCK1 SCK1 SI1 SI1 SO1 Input mode Output mode Input mode Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode 2 tsys + 200 16000/fc tsys + 100 8000/fc – 100 100 200 tsys + 200 100 tsys + 200 100 ns ns ns ns ns ns ns ns ns ns Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL. Serial transfer (CH1) (SIO mode) (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V) Item Symbol Pin Min. Max. Unit Condition SCK1 cycle time SCK1 high and low level widths SI1 input setup time (against SCK1 ↑) SI1 input hold time (against SCK1 ↑) SCK1 ↓→ SO1 delay time tKCY tKH tKL tSIK tKSI tKSO SCK1 SCK1 SI1 SI1 SO1 Input mode Output mode Input mode Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode 2 tsys + 200 16000/fc tsys + 100 8000/fc – 150 100 200 tsys + 200 100 tsys + 250 125 ns ns ns ns ns ns ns ns ns ns Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF. |
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