THC63LVDR84B_Rev.2.2_E

Copyright©2011 THine Electronics, Inc.

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THine Electronics, Inc.

THC63LVDR84B

LVDS 24Bit COLOR HOST-LCD PANEL INTERFACE RECEIVER (Rising Edge Clock)

General Description

The THC63LVDR84B receiver supports wide VCC

range(2.5~3.6V). A t single 2.5V suppl y, the

THC63LVDR84B reduces EMI and power consump-

tion.

The THC63LVDR84B receiver convert the four

LVDS(Low Voltage Differential Signaling) data streams

back into 24bits of CMOS/TTL data with rising edge

clock.

At a transmit clock frequency of 85MHz, 24bits of RGB

data an d 4b its of LC D timing an d co ntrol da ta

(HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at

a rate of 2.3Gbps.

Features

65MHz Grayscale

15 to 20

20 to 70

70 to 85

2.5 to 2.7

n/a

available

n/a

2.7 to 3.0 available available

n/a

3.0 to 3.6 available available available

n/a : not available

Clock Frequency[MHz]

VCC[V]

Block Diagram

PLL

RA +/-

RB +/-

RC +/-

RD +/-

RCLK +/-

/PDWN

RA0-6

RC0-6

RD0-6

RECEIVER

(15 to 85MHz)

CMOS/TTL

RB0-6

OUTPUT

CLOCK

(LVDS)

15 to 85MHz

DATA

(LVDS)

(105-595Mbit/On Each LVDS Channel)

7

7

7

7

CLOCK OUT

THC63LVDR84B