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ICX075AL 数据表(PDF) 2 Page - Sony Corporation |
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ICX075AL 数据表(HTML) 2 Page - Sony Corporation |
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2 / 21 page ![]() – 2 – ICX075AL Pin No. Pin No. Symbol Description Pin Description ∗1 DC bias is applied within the CCD, so that this pin should be grounded externally through a capacitance of 1µF or more. ∗2 Regarding the test pins: apply the same voltage as the supply voltage to HIS, and ground HIGφ 1 , HIG2, and POG φ. 1 2 3 4 5 6 7 8 9 10 11 VDD RG VL SUB H φ1 H φ2 HHG φ1 HHG φ2 HIG2 POG φ VOG φ Supply voltage Reset gate clock Protective transistor bias Substrate (overflow drain) Horizontal register transfer clock Horizontal register transfer clock Inter-horizontal register transfer clock Inter-horizontal register transfer clock Test pin ∗2 Test pin ∗2 Vertical register final stage transfer clock Test pin ∗2 Test pin ∗2 Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register final stage accumulation clock GND Output amplifier 1 gate ∗1 decoupling capacitor Signal output 1 Output amplifier 2 gate ∗1 decoupling capacitor Signal output 2 Symbol Description HIG φ1 HIS V φ3 V φ2 V φ1 VHOLD φ GND CGG1 VOUT1 CGG2 VOUT2 12 13 14 15 16 17 18 19 20 21 22 Horizontal Register 1 Horizontal Register 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Note) Note) : Photo sensor 15 16 17 18 19 20 21 22 Block Diagram and Pin Configuration (Top View) |
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