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WM8740SEDS/RV 数据表(PDF) 18 Page - Wolfson Microelectronics plc |
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WM8740SEDS/RV 数据表(HTML) 18 Page - Wolfson Microelectronics plc |
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18 / 27 page ![]() WM8740 Production Data w PD, Rev 4.4, April 2010 18 POLARITY OF LR INPUT CLOCK The left channel data for a particular sample instant is always input first, then the right channel data. LRP (REG3, B1) L LR High – left channel LR Low – right channel H LR Low – left channel LR High – right channel Table 12 Polarity of LR Input Clock INDIVIDUAL OR COMMON ATTENUTATION CONTROL ATC (REG3, B2) L Individual control H Common control from Reg0 Table 13 Individual or Common Attenuation Control DIGITAL FILTER ROLL-OFF SELECTION SRO (REG3, B3) L Sharp H Slow Table 14 Digital Filter Roll-Off Selection ANALOGUE OUTPUT POLARITY REVERSAL REV (REG3, B4) L Normal H Inverted Table 15 Analogue Output Polarity Reversal DE-EMPHASIS SAMPLE RATE SF1 (REG3, B7) SF0 (REG3, B6) SAMPLE RATE 0 0 No de-emphasis 0 1 48kHz 1 0 44.1kHz 1 1 32kHz Table 16 De-Emphasis Sample Rate INFINITE ZERO DETECT IZD (REG3, B8) L Zero detect mute off H Zero detect mute on Table 17 Infinite Zero Detect |
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