WM8940CGEFLSLASHV datasheet(65/91 Pages) WOLFSON

65 / 91 page

Production Data

WM8940

PD, Rev 4.3, November 2011

Figure 36 Alternative 3-Wire Serial Control Timing

A limited number of Readback addresses are provided to enable ALC operation to be monitored and

to establish the identity and revision of the device.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Software Reset

15:0

CHIP_ID

Readback the CHIP ID

Power

Management 1

2:0

DEVICE_REVIS

Readback the DEVICE_REVISON

Table 56 Readback Registers

2-WIRE SERIAL CONTROL MODE

The WM8940 supports software control via a 2-wire serial bus. Many devices can be controlled by

the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit

address of each register in the WM8940).

The WM8940 operates as a slave device only. The controller indicates the start of data transfer with

a high to low transition on SDIN while SCLK remains high. This indicates that a device address and

data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight

bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the

address of the WM8940, then the WM8940 responds by pulling SDIN low on the next clock pulse

(ACK). If the address is not recognised or the R/W bit is ‘1’ when operating in write only mode, the

WM8940 returns to the idle condition and wait for a new start condition and valid address.

During a write, once the WM8940 has acknowledged a correct address, the controller sends the first

byte of control data (B23 to B16, i.e. the WM8940 8 bit register address). The WM8940 then

acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends

the second byte of control data (B15 to B8, i.e. the most significant 8 bits of register data), and the

WM8940 acknowledges again by pulling SDIN low for one clock pulse. The controller then sends the

third byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8940

acknowledges again by pulling SDIN low for one clock pulse.

Transfers are complete when there is a low to high transition on SDIN while SCLK is high. After a

complete sequence the WM8940 returns to the idle state and waits for another start condition. If a

start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN

changes while SCLK is high), the device jumps to the idle condition.

Figure 37 2-Wire Serial Control Interface

In 2-wire mode the WM8940 has a fixed device address, 0011010.

WM8940CGEFL/V 数据表(PDF) 65 Page - Wolfson Microelectronics plc

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