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WM8946 数据表(PDF) 39 Page - Wolfson Microelectronics plc |
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WM8946 数据表(HTML) 39 Page - Wolfson Microelectronics plc |
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39 / 175 page  Production Data WM8946 w PD, July 2012, Rev 4.3 39 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R65 (41h) SE1_LHPF_C ONFIG 1 SE1_LHPF_R_E NA 0 SE1 Right channel low-pass / high- pass filter enable 0 = Disabled 1 = Enabled 0 SE1_LHPF_L_E NA 0 SE1 Left channel low-pass / high- pass filter enable 0 = Disabled 1 = Enabled R68 (44h) SE1_3D_CON FIG 1 SE1_3D_R_ENA 0 SE1 Right channel 3D stereo enhancement filter enable 0 = Disabled 1 = Enabled 0 SE1_3D_L_ENA 0 SE1 Left channel 3D stereo enhancement filter enable 0 = Disabled 1 = Enabled R71 (47h) SE1_NOTCH_ CONFIG 1 SE1_NOTCH_R _ENA 0 SE1 Right channel notch filters enable 0 = Disabled 1 = Enabled 0 SE1_NOTCH_L_ ENA 0 SE1 Left channel notch filters enable 0 = Disabled 1 = Enabled R92 (5Ch) SE1_DF1_CO NFIG 1 SE1_DF1_R_EN A 0 SE1 Right channel DF1 filter enable 0 = Disabled 1 = Enabled 0 SE1_DF1_L_EN A 0 SE1 Left channel DF1 filter enable 0 = Disabled 1 = Enabled Table 13 Signal Enhancement Block 1 (SE1) The SE2 ‘enable’ bits are described in Table 14. Note that (with the exception of the SE2 HPF) other control fields must also be determined and written to the WM8946 using WISCE™ or other tools. The registers described below only allow the sub-blocks of SE2 to be enabled or disabled. Note that it is not recommended to access these control fields unless appropriate values have been written to the associated bits in registers R99 to R175. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R100 (64h) SE2_RETUNE _CONFIG 1 SE2_RETUNE_ R_ENA 0 SE2 Right channel ReTune™ filter enable 0 = Disabled 1 = Enabled 0 SE2_RETUNE_ L_ENA 0 SE2 Left channel ReTune™ filter enable 0 = Disabled 1 = Enabled R133 (85h) SE2_5BEQ_C ONFIG 0 SE2_5BEQ_L_E NA 0 SE2 Left channel 5-band EQ enable 0 = Disabled 1 = Enabled Table 14 Signal Enhancement Block 2 (SE2) The register controls for Signal Enhancement Block SE3 are defined in the “Dynamic Range Control (DRC)” section. |
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