WM8948 datasheet(73/189 Pages) WOLFSON

73 / 189 page

Production Data

WM8948

PD, May 2011, Rev 4.1

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

Figure 23 Left Justified Audio Interface (assuming n-bit word length)

In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and

the MSB of the next.

Figure 24 I2S Justified Audio Interface (assuming n-bit word length)

In DSP/PCM mode, the left channel MSB is available on either the 1

st (mode B) or 2nd (mode A)

rising edge of BCLK (selected by LRCLK_INV) following a rising edge of LRCLK. Right channel data

immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,

there may be unused BCLK cycles between the LSB of the right channel data and the next sample.

In device master mode, the LRCLK output resembles the frame pulse shown in Figure 25 and Figure

26. In device slave mode, Figure 27 and Figure 28, it is possible to use any length of frame pulse

less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period

before the rising edge of the next frame pulse.

Figure 25 DSP/PCM Mode Audio Interface (mode A, LRCLK_INV=0, Master)

WM8948 数据表(PDF) 73 Page - Wolfson Microelectronics plc