– 7 –

ICX204AL

twh

tf

tr

90%

10%

twl

H

two

H

twl

RG waveform

tr

V

2

twh

tf

Point A

(3) Horizontal transfer clock waveform

(4) Reset gate clock waveform

V

V

Cross-point voltage for the H

The overlap period for twh and twl of horizontal transfer clocks H

Point A in the above diagram until the rising edge of RG.

V

(5) Substrate clock waveform

90%

100%

10%

0%

(A bias generated within the CCD)

tr

twh

tf

φM

φM

2

V