WM8352 datasheet(39/336 Pages) WOLFSON

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Production Data

WM8352

PD, February 2011, Rev 4.4

11.3 2-WIRE SERIAL CONTROL MODE

The 2-wire control interface normally uses the SCLK and SDATA pins, which are referenced to the

digital buffer supply, DBVDD. (In Development mode, the interface is initially redirected, with GPIO10

and GPIO11 effectively replacing SCLK and SDATA - see Section 14.4.1).

2-wire control mode is selected by setting SPI_3WIRE = 0. This is the default setting for this field.

In 2-wire mode, the WM8352 is a slave device on the control interface; SCLK (or GPIO10) is a clock

input, while SDATA (or GPIO11) is a bi-directional data pin. To allow arbitration of multiple slaves

(and/or multiple masters) on the same interface, the WM8352 transmits logic 1 by tri-stating the

SDATA pin, rather than pulling it high. An external pull-up resistor is required to pull the SDATA line

high so that the logic 1 can be recognised by the master.

Many devices can be controlled by the same bus, and each device has a unique 7-bit device ID (this

is not the same as the 8-bit address of each register in the WM8352). The default device ID is

0011 0100 (0x34h). The LSB of the device ID is the Read/Write bit; this bit is set to logic 1 for “Read”

and logic 0 for “Write”. In Development Mode, the device ID may be changed to other values.

The controller indicates the start of data transfer with a high to low transition on SDATA while SCLK

remains high. This indicates that a device ID, register address and data will follow. All devices on the

2-wire bus respond to the start condition and shift in the next eight bits on SDATA (7-bit device ID +

Read/Write bit, MSB first). If the device ID received matches the device ID of the WM8352, then the

WM8352 responds by pulling SDATA low on the next clock pulse (ACK). If the device ID is not

recognised or the R/W bit is ‘1’ when operating in write only mode, the WM8352 returns to the idle

condition and waits for a new start condition and valid address.

If the device ID matches the device ID of the WM8352, the data transfer continues as described

below. The controller indicates the end of data transfer with a low to high transition on SDATA while

SCKL remains high. After receiving a complete address and data sequence the WM8352 returns to

the idle state and waits for another start condition. If a start or stop condition is detected out of

sequence at any point during data transfer (i.e. SDATA changes while SCLK is high), the device

returns to the idle condition.

The WM8352 supports the following read and write operations:

•

Single write

•

Single read

•

Multiple write using auto-increment

•

Multiple read using auto-increment

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