05721

September 12, 2012

Rev: C

EP5348UI

©Enpirion 2012 all rights reserved, E&OE

9

www.enpirion.com

sensing point so that it does not interfere with

the control loop operation. Excess total

capacitance on the output (Output Filter + Bulk)

can cause an over-current condition at startup.

Please see the Soft Start section under

Functional

Overview

for

the

maximum

allowable bulk capacitance on the output rail.

The output capacitor must use a X5R or X7R

or equivalent dielectric formulation.

Y5V or

equivalent

dielectric

formulations

lose

capacitance

with

frequency,

bias,

and

temperature and are not suitable for switch-

mode

DC-DC

converter

output

filter

applications.

LDO Replacement

The

Enpirion

EP5348UI

is

a

suitable

replacement for inefficient LDOs and can be

used to augment the LDOs in a PMU with

minimum footprint impact.

This integrated

DCDC solution offers significantly better

efficiency, and significant reduction in power

loss.

The resulting improved thermals and

extended battery life helps meet Energy Star

requirements. The total solution size is 25%

smaller than a comparable LDO and half the

footprint of a comparable DCDC.

As the table below shows, EP5348UI provides

the optimal trade-off between footprint and

efficiency when compared to a traditional LDO:

Power-Up/Down Sequencing

During power-up, ENABLE should not be

asserted before PVIN, and PVIN should not be

asserted before AVIN. The PVIN should never

be powered when AVIN is off. During power

down, the AVIN should not be powered down

before the PVIN. Tying PVIN and AVIN or all

three pins (AVIN, PVIN, ENABLE) together

during power up or power down meets these

requirements

.

Pre-Bias Start-up

The EP5348UI does not support startup into a

pre-biased condition. Be sure the output

capacitors are not charged or the output of the

EP5348UI

is

not

pre-biased

when

the

EP5348UI is first enabled.

Layout Recommendations

Figure 4: Top PCB Layer Critical Components and

Copper for Minimum Footprint

Figure 5: Bottom PCB Layer Critical Components

VIN

(V)

VOUT

(V)

LOAD

(mA)

EFF

DCDC

EFF

LDO

PLOSS

DCDC

(mW)

PLOSS

LDO

(mW)

Power Saved

(mW)

5.0

1.2

400

70.4% 24.0%

202

1520

1318

5.0

1.8

400

76.4% 36.0%

222

1280

1058

5.0

2.5

400

81.6% 50.0%

225

1000

775

5.0

3.3

400

87.7% 66.0%

185

680

495

3.3

1.2

400

77.1% 36.4%

143

840

697

3.3

1.8

400

83.3% 54.5%

144

600

456

3.3

2.5

400

88.2% 75.8%

134

320

186