Constant-Current 3-Ampere PWM Dimmable

Buck Regulator LED Driver

A6211

14

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Component Placement and PCB Layout Guidelines

PCB layout is critical in designing any switching regulator. A

good layout reduces emitted noise from the switching device,

and ensures better thermal performance and higher efficiency.

The following guidelines help to obtain a high quality PCB

layout. Figure 15 shows an example for components placement.

Figure 16 shows the three critical current loops that should be

minimized and connected by relatively wide traces.

1) When the upper FET (integrated inside the A6211) is on, cur-

rent flows from the input supply/capacitors, through the upper

FET, into the load via the output inductor, and back to ground as

shown in loop 1. This loop should have relatively wide traces.

Ideally this connection is made on both the top (component) layer

and via the ground plane.

2) When the upper FET is off, free-wheeling current flows from

ground through the asynchronous diode D1, into the load via the

output inductor, and back to ground as shown in loop 2. This loop

should also be minimized and have relatively wide traces. Ideally

this connection is made on both the top (component) layer and

via the ground plane.

3) The highest di/dt occurs at the instant the upper FET turns on

and the asynchronous diode D1 undergoes reverse recovery as

shown in loop 3. The ceramic input capacitors C2 must deliver

this high instantaneous current. C1 (electrolytic capacitor) should

not be too far off C2. Therefore, the loop from the ceramic input

capacitor through the upper FET and asynchronous diode to

ground should be minimized. Ideally this connection is made on

both the top (component) layer and via the ground plane.

4) The voltage on the SW node (pin 8) transitions from 0 V to

the asynchronous diode and output inductor close to the A6211 to

minimize the size of the SW polygon.

Keep sensitive analog signals (CS, and R1 of switching fre-

quency setting) away from the SW polygon.

6) For accurate current sensing, the LED current sense resistor

7) Place the boot strap capacitor C4 near the BOOT node (pin 7)

and keep the routing to this capacitor short.

8) When routing the input and output capacitors (C1, C2, and C3

if used), use multiple vias to the ground plane and place the vias

as close as possible to the A6211 pads.

9) To minimize PCB losses and improve system efficiency, the

input (VIN) and output (VOUT) traces should be wide and dupli-

cated on multiple layers, if possible.

Figure 16. Three different current loops in a buck converter

Figure 15. Example layout for the A6211 evaluation board

D1

L1

LED

SW

Loop 2

Loop 1

Loop 3