2 (15)

DA6181B.002

5 May, 2011

PAD LAYOUT

1120 µ

µ

µ

µ

m

MAS6181B1

VDD

QO2

QO1

QI

AGC

PDN2

OUT

VSS

RFI2

RFIM

RFIP

PDN1

AON

DEC

1st bond!

Do not bond!

DIE size = 1120 x 1530 µm; rectangular PAD 80 µm x 80 µm

Note: Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left

floating. Please make sure that VSS is the first pad to be bonded. Pick-and-place and all component assembly

are recommended to be performed in ESD protected area.

Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die.

Pad Identification

Name

X-coordinate

Y-coordinate

Note

Power Supply Voltage

VDD

126 µm

1332 µm

Quartz Filter Output for Crystal 2

QO2

126 µm

1132 µm

Quartz Filter Output for Crystal 1

QO1

126 µm

962 µm

Quartz Filter Input for Crystals

QI

126 µm

788 µm

AGC Capacitor

AGC

126 µm

614 µm

Power Down/Frequency Selection Input 2

PDN2

126 µm

440 µm

1

Receiver Output

OUT

126 µm

263 µm

2

Demodulator Capacitor

DEC

994 µm

266 µm

AGC On Control

AON

994 µm

450 µm

3

Power Down/Frequency Selection Input 1

PDN1

994 µm

618 µm

1

Positive Receiver Input

RFIP

994 µm

807 µm

4

Negative Receiver Input

RFIM

994 µm

985 µm

4

Test pad RFIMB

RFIMB

298 µm

1025 µm

5

Test pad RFI2B

RFI2B

400 µm

1025 µm

5

Receiver Input 2 (for Antenna Capacitor 2)

RFI2

994 µm

1163 µm

Power Supply Ground

VSS

994 µm

1321 µm

Notes:

1) PDN1 = VDD and PDN2 = VDD means receiver off

-

Fast start-up is triggered when the receiver is after power down controlled to power on

2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced

(modulated)

-

-

At power down the output is pulled to VSS (pull down switch)

3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (normal operation)

-

Unused AON pad can be left unconnected due to internal pull-up with current < 1 µA. Pull up current is

switched off at power down.

4) Receiver inputs RFIP and RFIM have both 1.4 MΩ biasing resistors towards VDD

5) RFIMB and RFI2B pads are left unconnected. They are only for wafer level testing purposes