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AD5204/AD5206–SPECIFICATIONS

–2–

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Conditions

Min

Typ1

Max

Units

DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs

Resistor Differential NL2

R-DNL

RWB, VA = No Connect

–1

± 1/4

LSB

Resistor Nonlinearity Error2

R-INL

RWB, VA = No Connect

–2

± 1/2

LSB

Nominal Resistor Tolerance3

∆R

TA = +25°C

–30

+30

Resistance Temperature Coefficient

∆R

AB/∆TVAB = VDD, Wiper = No Connect

700

ppm/

°C

Nominal Resistance Match

∆R/R

CH1 to 2, 3, 4, or 5, 6; VAB = VDD

0.25

1.5

Wiper Resistance

IW = 1 V/R, VDD = +5 V

100

Ω

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs

Resolution

Bits

Differential Nonlinearity4

DNL

–1

± 1/4

LSB

Integral Nonlinearity4

INL

–2

± 1/2

LSB

Voltage Divider Temperature Coefficient

∆V

W/∆T

Code = 40H

ppm/

°C

Full-Scale Error

VWFSE

Code = 7FH

–2

–1

LSB

Zero-Scale Error

VWZSE

Code = 00H

0+1

LSB

RESISTOR TERMINALS

Voltage Range5

VA, VB, VW

VSS

VDD

Capacitance6 Ax, Bx

CA, CB

f = 1 MHz, Measured to GND, Code = 40H

Capacitance6 Wx

f = 1 MHz, Measured to GND, Code = 40H

Shutdown Current7

IA_SD

0.01

µA

Common-Mode Leakage

ICM

VA = VB = VW = 0, VDD = +2.7 V, VSS = –2.5 V

DIGITAL INPUTS AND OUTPUTS

Input Logic High

VIH

VDD = +5 V/+3 V

2.4/2.1

Input Logic Low

VIL

VDD = +5 V/+3 V

0.8/0.6

Output Logic High

VOH

RPULL–UP = 1 kΩ to +5 V

4.9

Output Logic Low

VOL

IOL = 1.6 mA, VLOGIC = +5 V

0.4

Input Current

IIL

VIN = 0 V or +5 V

± 1

µA

Input Capacitance

CIL

5pF

POWER SUPPLIES

Power Single Supply Range

VDD Range

VSS = 0 V

2.7

5.5

Power Dual Supply Range

VDD/SS Range

± 2.3

± 2.7

Positive Supply Current

IDD

VIH = +5 V or VIL = 0 V

µA

Negative Supply Current

ISS

VSS = –2.5 V, VDD = +2.7 V

µA

Power Dissipation

PDISS

VIH = +5 V or VIL = 0 V

0.3

Power Supply Sensitivity

PSS

∆V

DD = +5 V

± 10%

0.0002

0.005

%/%

DYNAMIC CHARACTERISTICS

6, 9

Bandwidth –3 dB

BW_10K

RAB = 10 k

Ω

721

kHz

BW_50K

RAB = 50 k

Ω

137

kHz

BW_100K

RAB = 100 k

Ω

kHz

Total Harmonic Distortion

THDW

VA = 1.414 V rms, VB = 0 V dc, f = 1 kHz

0.004

VW Settling Time (10K/50K/100K)

VA = 5 V, VB = 0 V,

± 1 LSB Error Band

2/9/18

µs

Resistor Noise Voltage

eN_WB

RWB = 5 k

Ω, f = 1 kHz, PR = 0

nV/

√Hz

INTERFACE TIMING CHARACTERISTICS Applies to All Parts

6, 10

Input Clock Pulsewidth

tCH, tCL

Clock Level High or Low

Data Setup Time

tDS

5ns

Data Hold Time

tDH

5ns

CLK to SDO Propagation Delay

tPD

RL = 2 k

Ω, C

L < 20 pF

150

CS Setup Time

tCSS

CS High Pulsewidth

tCSW

Reset Pulsewidth

tRS

CLK Fall to

CS Fall Setup

tCSH0

0ns

CLK Fall to

CS Rise Hold Time

tCSH1

0ns

CS Rise to Clock Rise Setup

tCS1

NOTES

1Typicals represent average readings at +25

°C and V

DD = +5 V.

2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-

tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 23 test circuit. I W = VDD/R

for both VDD = +3 V or VDD = +5 V.

AB = VDD, Wiper (VW) = No connect.

4INL and DNL are measured at V

W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V.

DNL specification limits of

±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 22 test circuit.

(VDD = +5 V

10% or +3 V

10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40 C < TA < +85 C

unless otherwise noted.)

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