AD5301 datasheet(2/15 Pages) AD

2 / 15 page

REV. 0

–2–

AD5301/AD5311/AD5321–SPECIFICATIONS (V

DD = +2.5 V to +5.5 V; RL = 2 k

to GND;

CL = 200 pF to GND; All specifications TMIN to TMAX unless otherwise noted.)

B Version2

Parameter1

Min

Typ

Max

Units

Conditions/Comments

DC PERFORMANCE3, 4

AD5301

Resolution

Bits

Relative Accuracy

±0.15

±1

LSB

Differential Nonlinearity

±0.02

±0.25

LSB

Guaranteed Monotonic by Design Over All Codes

AD5311

Resolution

Bits

Relative Accuracy

±0.5

±4

LSB

Differential Nonlinearity

±0.05

±0.5

LSB

Guaranteed Monotonic by Design Over All Codes

AD5321

Resolution

Bits

Relative Accuracy

±2

±16

LSB

Differential Nonlinearity

±0.3

±0.8

LSB

Guaranteed Monotonic by Design Over All Codes

Zero Code Error

+20

All Zeros Loaded to DAC, See Figure 9

Full-Scale Error

±0.15

±1.25

% of FSR

All Ones Loaded to DAC, See Figure 9

Gain Error

±0.15

±1

% of FSR

Zero Code Error Drift5

–20

µV/°C

Gain Error Drift5

–5

ppm of FSR/

°C

OUTPUT CHARACTERISTICS

Minimum Output Voltage

0.001

V min

This is a measure of the minimum and maximum drive

Maximum Output Voltage

VDD – 0.001

V max

capability of the output amplifier.

DC Output Impedance

Ω

Short Circuit Current

VDD = +5 V

VDD = +3 V

Power-Up Time

2.5

µs

Coming Out of Power-Down Mode. VDD = +5 V

µs

Coming Out of Power-Down Mode. VDD = +3 V

LOGIC INPUTS (A0, A1,

PD)5

Input Current

±1

µA

VIL, Input Low Voltage

0.8

VDD = +5 V ± 10%

0.6

VDD = +3 V ± 10%

0.5

VDD = +2.5 V

VIH, Input High Voltage

2.4

VDD = +5 V ± 10%

2.1

VDD = +3 V ± 10%

2.0

VDD = +2.5 V

Pin Capacitance

LOGIC INPUTS (SCL, SDA)5

VIH, Input High Voltage

0.7 VDD

VDD + 0.3 V

VIL, Input Low Voltage

–0.3

0.3 VDD

IIN, Input Leakage Current

±1

µAV

IN = 0 V to VDD

VHYST, Input Hysteresis

0.05 VDD

CIN, Input Capacitance

Glitch Rejection6

Pulsewidth of Spike Suppressed

LOGIC OUTPUT (SDA)

VOL, Output Low Voltage

0.4

ISINK = 3 mA

0.6

ISINK = 6 mA

Three-State Leakage Current

±1

µA

Three-State Output Capacitance

POWER REQUIREMENTS

VDD

2.5

5.5

IDD Specification Is Valid for All DAC Codes

IDD (Normal Mode)

DAC Active and Excluding Load Current

VDD = +4.5 V to +5.5 V

150

250

µAV

IH = VDD and VIL = GND

VDD = +2.5 V to +3.6 V

120

220

µAV

IH = VDD and VIL = GND

IDD (Power-Down Mode)

VDD = +4.5 V to +5.5 V

0.2

µAV

IH = VDD and VIL = GND

VDD = +2.5 V to +3.6 V

0.05

µAV

IH = VDD and VIL = GND

NOTES

1See Terminology.

2Temperature ranges are as follows: B Version: –40

°C to +105°C.

3DC specifications tested with the outputs unloaded.

4Linearity is tested using a reduced code range: AD5301 (Code 7 to 250); AD5311 (Code 28 to 1000); AD5321 (Code 112 to 4000).

5Guaranteed by Design and Characterization, not production tested.

6Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.

Specifications subject to change without notice .

AD5301 数据表(PDF) 2 Page - Analog Devices

AD5301 数据表(HTML) 2 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

数据表下载

链接网址

AD5301 数据表(PDF) 2 Page - Analog Devices

AD5301 数据表(HTML) 2 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

数据表 下载

链接网址

数据表下载