REV. 0

AD5303/AD5313/AD5323

–13–

contents of the input registers. In the case of the AD5303/AD5313/

AD5323, the part will only update the DAC register if the input

register has been changed since the last time the DAC register

was updated thereby removing unnecessary digital crosstalk.

POWER-DOWN MODES

The AD5303/AD5313/AD5323 have very low power consump-

tion, dissipating only 0.7 mW with a 3 V supply and 1.5 mW

with a 5 V supply. Power consumption can be further reduced

when the DACs are not in use by putting them into one of three

power-down modes, which are selected by Bits 13 and 12 (PD1

and PD0) of the control word. Table II shows how the state of

the bits corresponds to the mode of operation of that particular

DAC.

Table II. PD1/PD0 Operating Modes

PD1

PD0

Operating Mode

0

0

Normal Operation

0

1

Power-Down (1 k

Ω Load to GND)

1

0

Power-Down (100 k

Ω Load to GND)

1

1

Power-Down (High Impedance Output)

When both bits are set to 0, the DACs work normally with their

normal power consumption of 300

µA at 5 V. However, for the

three power-down modes, the supply current falls to 200 nA at

5 V (50 nA at 3 V) when both DACs are powered down. Not

only does the supply current drop but the output stage is also

internally switched from the output of the amplifier to a resistor

network of known values. This has the advantage that the out-

put impedance of the part is known while the part is in power-

down mode and provides a defined input condition for whatever

is connected to the output of the DAC amplifier. There are

three different options. The output is connected internally to

GND through a 1 k

Ω resistor, a 100 kΩ resistor or it is left in a

high impedance state (Three-State). The output stage is illus-

trated in Figure 32.

The bias generator, the output amplifier, the resistor string and

all other associated linear circuitry are all shut down when the

power-down mode is activated. However, the contents of the

registers are unaffected when in power-down. The time to exit

power-down is typically 2.5

µs for V

µs when

The software power-down modes programmed by PD0 and

PD1 are overridden by the PD pin. Taking this pin low puts

both DACs into power-down mode simultaneously and both

outputs are put into a high impedance state. If PD is not used it

should be tied high.

AMPLIFIER

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

RESISTOR

STRING DAC

Figure 32. Output Stage During Power-Down

MICROPROCESSOR INTERFACING

AD5303/AD5313/AD5323 to ADSP-2101/ADSP-2103 Interface

Figure 33 shows a serial interface between the AD5303/AD5313/

AD5323 and the ADSP-2101/ADSP-2103. The ADSP-2101/

ADSP-2103 should be set up to operate in the SPORT Trans-

mit Alternate Framing Mode. The ADSP-2101/ADSP-2103

SPORT is programmed through the SPORT control register

and should be configured as follows: Internal Clock Operation,

Active-Low Framing, 16-Bit Word Length. Transmission is

initiated by writing a word to the Tx register after the SPORT

has been enabled.

SCLK

DIN

SYNC

TFS

DT

SCLK

ADSP-2101/

ADSP-2103*

*ADDITIONAL PINS OMITTED FOR CLARITY.

AD5303/

AD5313/

AD5323*

Figure 33. AD5303/AD5313/AD5323 to ADSP-2101/ADSP-

2103 Interface

AD5303/AD5313/AD5323 to 68HC11/68L11 Interface

Figure 34 shows a serial interface between the AD5303/AD5313/

AD5323 and the 68HC11/68L11 microcontroller. SCK of the

68HC11/68L11 drives the SCLK of the AD5303/AD5313/

AD5323, while the MOSI output drives the serial data line

(DIN) of the DAC. The SYNC signal is derived from a port line

(PC7). The setup conditions for correct operation of this inter-

face are as follows: the 68HC11/68L11 should be configured so

that its CPOL bit is a 0 and its CPHA bit is a 1. When data is

being transmitted to the DAC, the SYNC line is taken low

(PC7). When the 68HC11/68L11 is configured as above, data

appearing on the MOSI output is valid on the falling edge of

SCK. Serial data from the 68HC11/68L11 is transmitted in

8-bit bytes with only eight falling clock edges occurring in the

transmit cycle. Data is transmitted MSB first. In order to load

data to the AD5303/AD5313/AD5323, PC7 is left low after the

first eight bits are transferred, a second serial write operation is

performed to the DAC and PC7 is taken high at the end of this

procedure.

DIN

SCLK

SYNC

PC7

SCK

MOSI

68HC11/68L11*

*ADDITIONAL PINS OMITTED FOR CLARITY.

AD5303/

AD5313/

AD5323*

Figure 34. AD5303/AD5313/AD5323 to 68HC11/68L11

Interface