REV. B

AD536A

–5–

factors, (such as low duty cycle pulse trains), the averaging time

constant should be at least ten times the signal period. For

example, a 100 Hz pulse rate requires a 100 ms time constant,

which corresponds to a 4

µF capacitor (time constant = 25 ms

per

µF).

is that the settling time for a step change in input level is in-

creased proportionately. Figure 5 shows that the relationship

creasing signals as for increasing signals (the values in Figure 5

are for decreasing signals). Settling time also increases for low

signal levels, as shown in Figure 6.

Figure 5. Error/Settling Time Graph for Use with the Stan-

dard rms Connection in Figure 1

Figure 6. Settling Time vs. Input Level

A better method for reducing output ripple is the use of a

“post-filter.” Figure 7 shows a suggested circuit. If a single-pole

µF

and C2 = 2.2

µF, the ripple for a 60 Hz input is reduced from

10% of reading to approximately 0.3% of reading. The settling

time, however, is increased by approximately a factor of 3. The

settling times while still providing substantial ripple reduction.

The two-pole post-filter uses an active filter stage to provide

even greater ripple reduction without substantially increasing

the settling times over a circuit with a one-pole filter. The values

settling times for a constant amount of ripple. Caution should

dependent upon this value and is independent of the post filter.

For a more detailed explanation of these topics refer to the

RMS to DC Conversion Application Guide 2nd Edition, available

from Analog Devices.

C2

C3

C3

Figure 7. 2-Pole “Post” Filter

Figure 8. Performance Features of Various Filter Types

AD536A PRINCIPLE OF OPERATION

The AD536A embodies an implicit solution of the rms equation

that overcomes the dynamic range as well as other limitations

inherent in a straightforward computation of rms. The actual

computation performed by the AD536A follows the equation:

Vrms

= Avg .

V

IN

2

Vrms

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