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AD5541/AD5542

–3–

REV. A

SCLK

DIN

DB15

LDAC*

DB0

*AD5542 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.

t11

t10

t12

Figure 1. Timing Diagram

TIMING CHARACTERISTICS1, 2

Limit at TMIN, TMAX

Parameter

All Versions

Unit

Description

fSCLK

MHz max

SCLK Cycle Frequency

ns min

SCLK Cycle Time

ns min

SCLK High Time

ns min

SCLK Low Time

ns min

CS Low to SCLK High Setup

ns min

CS High to SCLK High Setup

ns min

SCLK High to CS Low Hold Time

ns min

SCLK High to CS High Hold Time

ns min

Data Setup Time

ns min

Data Hold Time

t10

ns min

LDAC Pulsewidth

t11

ns min

CS High to LDAC Low Setup

t12

ns min

CS High Time Between Active Periods

NOTES

1Guaranteed by design. Not production tested.

2Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to

90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

Speciﬁcations subject to change without notice.

(VDD = 5 V

5%, VREF = 2.5 V, AGND = DGND = 0 V. All speciﬁcations TA = TMIN to TMAX, unless

otherwise noted.)

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