AD604

REV. 0

–14–

The signal is applied to connector VIN, and since the signal

source was 50

Ω, a terminating resistor (R1) of 50 Ω was added.

The signal is then amplified by 14 dB (Pin FBK1 shorted to

PAO1) through the Channel 1 preamplifier, and is further pro-

cessed by the Channel 1 DSX. Next the signal is applied directly

to the Channel 2 DSX. The second preamplifier is powered

down by connecting its COM2 pin to the positive supply as

explained in the preamplifier section earlier. Capacitors C1 and

C2 level shift the signal from the preamplifier into the first DSX

and at the same time eliminate any offset contribution of the

preamp. C3 and C4 have the same offset cancellation purpose

for the second DSX. Each set of capacitors together with the

175

Ω input resistance of the corresponding DSX provides a

high pass filter with –3 dB corner frequency of about 9.1 kHz.

Pin VOCM is decoupled to ground by a 0.1

µF capacitor, while

VREF can be externally provided; in this application the gain

scale is set to 20 dB/V by applying 2.500 V. Since each of the

DSX amplifiers operates from a single +5 V supply, the output

is ac coupled via C6 and C7. The output signal can be moni-

tored at the connector labeled RF OUT.

Figures 43 and 44 show the gain range and gain error for the

AD604 connected as shown. The gain range is –14 dB to +82 dB;

the useful range is 0 dB to +82 dB if the RF output amplitude is

controlled to

±400 mV (+2 dBm). The main limitation on the

lower end of the signal range is the input capability of the

VGN – Volts

90

80

–30

70

60

20

50

40

30

–20

–10

0

10

1.7

0.1

0.5

0.9

1.3

2.1

2.5

2.9

f = 1MHz

Figure 43. AD604 Cascaded Gain vs. VGN

VGN – Volts

4

3

–4

2.2

2

1

–3

0

–1

–2

0.2

0.7

1.2

1.7

2.7

f = 1MHz

Figure 44. AD604 Cascaded Gain Error vs. VGN

preamplifier. This can be overcome by adding an attenuator in

front of the preamplifier, but that would defeat the advantage of

the ultralow noise preamplifier. It should be noted that the sec-

ond preamplifier is not used since its ultralow noise and the

associated high power consumption are overkill after the first

DSX stage. It is disabled in this application by connecting the

COM2 pin to the positive supply. Nevertheless, the second

preamplifier can be used if so desired and the useful gain range

will shift up by 14 dB, to encompass 0 dB to +96 dB of gain.

For the same +2 dBm output this would allow signals as small

as –94 dBm to be measured.

To achieve the highest gains, the input signal has to ultimately

be bandlimited to reduce the noise; this is especially true if the

second preamplifier is used. If the maximum signal at Pin OUT2

of the AD604 is limited to be

±400 mV (+2 dBm), then the in-

put signal level at the AGC threshold is 25

µV rms (–79 dBm).

The circuit as shown has about 40 MHz of noise bandwidth; the

0.8 nV/

√Hz of input referred voltage noise spectral density of

the AD604 results in an rms noise of 5.05

µV in the 40 MHz

bandwidth. The 50

Ω termination resistor, together with the

50

Ω source resistance of the signal generator, combine to an

effective resistance as seen by the input of the preamplifier of

25

Ω which makes 4.07 µV of rms noise in 40 MHz. The noise

floor of this channel is consequently the rms sum of these two

main noise sources, 6.5

µV rms. This means that the minimum

dectectable signal (MDS) for this circuit is 6.5

µV rms

(–90.7 dBm). As a general rule of thumb the measured signal

should be about a factor-of-three larger than the noise floor, in

this case 19.5

µV rms. As we can see the 25 µV rms signal that

this AGC circuit can correct for is just slightly above the MDS.

Of course, the sensitivity of the input can be improved by

bandlimiting the signal; if the noise bandwidth is reduced by a

factor-of-four to 10 MHz, the noise floor of the AGC circuit

with 50

Ω termination resistor will drop to 3.25 µV rms

(–96.7 dBm). Further noise improvement can be achieved by an

input matching network or by transformer coupling of the input

signal.

Next we will describe the functioning of the detector circuitry

comprised of a squarer, a low-pass filter, and an integrator. At

this point it is necessary to make some assumptions about the

input signal. The following explanation of the detector circuitry

presumes an amplitude modulated RF carrier where the modu-

lating signal is at a much lower frequency than the RF signal.

The AD835 multiplier functions as the detector by squaring the

output signal presented to it by the AD604. A low-pass filter fol-

lowing the squaring operation removes the RF signal component

at twice the incoming signal frequency, while passing the low

frequency AM information. The following integrator with a time

constant of 2 ms set by R8 and C11 integrates the error signal

presented by the low-pass filter and changes VG until the error

For example, if the signal presented to the detector is V1 =

A*cos(

ωt) as indicated in Figure 42, then the output of the

squarer is –(V1)

detection circuitry comes from the necessity of providing nega-

greater-than 0 V, the control loop provides positive feedback.

Squaring A*cos(

ωt) results in two terms, one at dc and one at

2