a

Low Power Mixer/Limiter/RSSI

3 V Receiver IF Subsystem

AD608

© Analog Devices, Inc., 1996

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

FEATURES

Mixer

–15 dBm 1 dB Compression Point

–5 dBm IP3

24 dB Conversion Gain

>500 MHz Input Bandwidth

Logarithmic/Limiting Amplifier

80 dB RSSI Range

3 Phase Stability over 80 dB Range

Low Power

21 mW at 3 V Power Consumption

CMOS-Compatible Power-Down to 300

W typ

200 ns Enable/Disable Time

APPLICATIONS

PHS, GSM, TDMA, FM, or PM Receivers

Battery-Powered Instrumentation

Base Station RSSI Measurement

The RF and LO bandwidths both exceed 500 MHz. In a typical

IF application, the AD608 will accept the output of a 240 MHz

SAW filter and downconvert it to a nominal 10.7 MHz IF with

Ω). The AD608’s loga-

rithmic/limiting amplifier section handles any IF from LF to as

high as 30 MHz.

The mixer is a doubly-balanced “Gilbert-Cell” type and oper-

ates linearly for RF inputs spanning –95 dBm to –15 dBm. It

has a nominal –5 dBm third-order intercept. An onboard LO

preamplifier requires only –16 dBm of LO drive. The mixer’s

current output drives a reverse-terminated, industry-standard

10.7 MHz 330

Ω filter.

The nominal logarithmic scaling is such that the output is

+0.2 V for a sinusoidal input to the IF amplifier of –75 dBm

and +1.8 V at an input of +5 dBm; over this range the logarith-

mic conformance is typically

±1 dB. The logarithmic slope is

proportional to the supply voltage. A feedback loop automati-

cally nulls the input offset of the first stage down to the sub-

microvolt level.

The AD608’s limiter output provides a hard-limited signal out-

put at 400 mV p-p. The voltage gain of the limiting amplifier to

this output is more than 100 dB. Transition times are 11 ns and

the phase is stable to within

±3° at 10.7 MHz for signals from

–75 dBm to +5 dBm.

The AD608 is enabled by a CMOS logic-level voltage input,

with a response time of 200 ns. When disabled, the standby

power is reduced to 300

µW within 400 ns.

The AD608 is specified for the industrial temperature range of

–25

°C to +85°C for 2.7 V to 5.5 V supplies and –40°C to +85°C

for 4.5 V to 5.5 V supplies. It comes in a 16-pin plastic SOIC.

GENERAL DESCRIPTION

The AD608 provides both a low power, low distortion, low

noise mixer and a complete, monolithic logarithmic/limiting

amplifier using a “successive-detection” technique. It provides

both a high speed RSSI (Received Signal Strength Indicator)

output with 80 dB dynamic range and a hard-limited output.

The RSSI output is from a two-pole post-demodulation low-

pass filter and provides a loadable output voltage of +0.2 V to

+1.8 V. The AD608 operates from a single 2.7 V to 5.5 V sup-

ply at a typical power level of 21 mW at 3 V.

FUNCTIONAL BLOCK DIAGRAM

24dB MIXER GAIN

110dB LIMITER GAIN

90dB RSSI

BIAS

MXOP

MIXER

BPF

DRIVER

VMID

LO

PREAMP

AD608

RFHI

RFLO

IF INPUT

–75dBm TO

IFHI

IFLO

LMOP

VPS2

RSSI

FDBK

COM3

FINAL

LIMITER

100nF

10nF

330

Ω

±50µA

330

Ω

MID-SUPPLY

IF BIAS

5

7

8

10

9

13

14

12

11

2

4

16

LIMITER

OUTPUT

400mVp-p

PRUP

RF INPUT

–95 TO

VPS1 COM1

COM2

LOHI

RSSI OUTPUT

20mV/dB

0.2V TO 1.8V

3dB NOMINAL

INSERTION LOSS

+2.7V TO 5.5V

5-STAGE IF AMPLIFIER

(16dB PER STAGE)

7 FULL-WAVE

RECTIFIER CELLS

≈

+2.7V TO

5.5V

LO INPUT

–16dBm

CMOS LOGIC

INPUT

±6mA MAX OUTPUT

(

±890mV INTO 165Ω)

100

Ω

18nF

±56mV MAX FOR LINEAR OPERATION

2MHz

LPF

15

1

3

6

±1dB RSSI

ACCURACY

NOTES:

10.7MHz

BANDPASS

FILTER

≈

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.