REV. C

AD641

–7–

Transistors Q3 through Q6 form the full wave detector, whose

output is buffered by the cascodes Q9 and Q10. For zero input

Q3 and Q5 conduct only a small amount (a total of about 32

µA)

of the 565

µA tail currents supplied to pairs Q3–Q4 and Q5–Q6.

This “pedestal” current flows in output cascode Q9 to the LOG

OUT node (Pin 14). When driven to the peak output of the

preceding stage, Q3 or Q5 (depending on signal polarity) con-

ducts most of the tail current, and the output rises to 532

µA.

The LOG OUT current has thus changed by 500

µA as the

input has changed from zero to its maximum value. Since the

detectors are spaced at 10 dB intervals, the output increases by

50

µA/dB, or 1 mA per decade. This scaling parameter is trimmed

to absolute accuracy using a 2 kHz square wave. At frequencies

near the system bandwidth, the slope is reduced due to the

reduced output of the limiter stages, but it is still relatively in-

sensitive to temperature variations so that a simple external

slope adjustment can restore scaling accuracy.

The intercept position bias generator (Figure 17) removes the

pedestal current from the summed detector outputs. It is ad-

justed during manufacture such that the output (flowing into

Pin 14) is 1 mA when a 2 kHz square-wave input of exactly

±10 mV is applied to the AD641. This places the dc intercept at

precisely 1 mV. The LOG COM output (Pin 13) is the comple-

ment of LOG OUT. It also has a 1 mV intercept, but with an

inverted slope of –1 mA/decade. Because its pedestal is very

large (equivalent to about 100 dB), its intercept voltage is not

guaranteed. The intercept positioning currents include a special

internal temperature compensation (ITC) term which can be

disabled by connecting Pin 8 to ground.

The logarithmic function of the AD641 is absolutely calibrated

to within

±0.3 dB (or ±15 µA) for 2 kHz square-wave inputs of

±1 mV to ±100 mV, and to within ±1 dB between ±750 µV and

±200 mV. Figure 18 is a typical plot of the dc transfer function,

2.5

–0.5

1000.0

0.5

0

1.0

0.1

1.0

1.5

2.0

100.0

10.0

INPUT VOLTAGE – mV

2

1

0

–1

–2

3

–55 C

+125 C

+25 C

+125 C

–55 C

+25 C

Figure 18. Logarithmic Output and Absolute Error vs. DC

Input Direct to Pins 1 and 20

2.5

–0.5

10000

0.5

0

10

0.1

1.0

1.5

2.0

1000

100

INPUT VOLTAGE – mV

1

0

–1

–2

+25 C

–55 C

+85 C

+125 C

Figure 19. Logarithmic Output and Absolute Error vs. DC

+125

°C. Input via On-Chip Attenuator

showing the outputs at temperatures of –55

°C, +25°C and

+125

°C. While the slope and intercept are seen to be little af-

fected by temperature, there is a lateral shift in the end points of

the “linear” region of the transfer function, which reduces the

effective dynamic range.

The on chip attenuator can be used to handle input levels 20 dB

higher, that is, from

±7.5 mV to ±2 V for dc or square wave

inputs. It is specially designed to have a positive temperature

coefficient and is trimmed to position the intercept at 10 mV dc

(or –24 dBm for a sinusoidal input) over the full temperature

range. When using the attenuator the internal bias compensa-

tion should be disabled by grounding Pin 8. Figure 19 shows

the output at –55

°C, +25°C, +85°C and +125°C for a single,

AD641 with the attenuator in use; the curves overlap almost

perfectly, and the lateral shift in the transfer function does not

occur. Therefore, the full dynamic range is available at all

temperatures.

The output of the final limiter is available in differential form at

Pins 10 and 11. The output impedance is 75

Ω to ground from

either pin. For most input levels, this output will appear to have

roughly a square waveform. The signal path may be extended

using these outputs (see OPERATION OF CASCADED

AD641s). The logarithmic outputs from two or more AD641s

can be directly summed with full accuracy.

A pair of 1 k

Ω applications resistors, RG1 and RG2 (Figure 17)

are accessed via Pins 15, 16 and 17. These can be used to con-

vert an output current to a voltage, with a slope of 1 V/decade

(using one resistor), 2 V/decade (both resistors in series) or

0.5 V/decade (both in parallel). Using all the resistors from two

AD641s (for example, in a cascaded configuration) ten slope

options from 0.25 V to 4 V/decade are available.