CS1630 datasheet(19/56 Pages) APEX

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CS1630/31

DS954F2

5.8.6 Output Open Circuit Protection

Output open circuit protection and output overvoltage

protection (OVP) are implemented by monitoring the output

voltage through the second-stage inductor auxiliary winding.

Overvoltage protection is enabled by setting bit OVP to ‘0’ in

79" on page 41). If the voltage on the FBAUX pin exceeds a

threshold (VOVP(th)) of 1.25V during the time the second stage

gate drive is turned ‘OFF’ and outside of the blanking window

configured by bit OVP_TYPE and bits OVP_BLANK[2:0] in

82" on page 43), then the OVP event accumulator is

incremented by 1 before the start of the next switching cycle.

If the OVP comparator threshold is not exceeded during the

switching cycle, the event accumulator is decremented by 1. If

the event accumulator count exceeds or equals the count set

by bits OVP_CNT[2:0] in register Config50 then an OVP fault

is declared and enters a fault state.

The fault state is latched if bit OVP_LAT in register Config50

is set high. The OVP fault state is not cleared until the power

to the IC is recycled. Otherwise, if bit OVP_LAT is set low, the

system is restarted after a specified amount of time configured

by using the bit FAULT_SLOW and bits RESTART[5:0] in

83" on page 43). The fault behavior during the fault state

initiated by this protection depends on the setting for bit

FAULT_SHDN in register Config51.

5.8.7 Overcurrent Protection

Overcurrent protection (OCP) is implemented by monitoring

the voltage across the second-stage sense resistor.

Overcurrent protection is enabled by setting bit OCP to ‘0’ in

79" on page 41). If this voltage exceeds a threshold (VOCP(th))

of 1.69V during the time the second stage gate drive is turned

‘ON’ and outside of the blanking window configured by bits

OCP_BLANK[2:0] in register Config48 (see "Configuration 48

(Config48) – Address 80" on page 42), then the OCP event

accumulator is incremented by 1 after the gate drive turns

‘OFF’. If the OCP comparator threshold is not exceeded

during this time, the event accumulator is decremented by 1.

If the event accumulator count exceeds or equals the count

set by bits OCP_CNT[2:0] in register Config49 (see

"Configuration 49 (Config49) – Address 81" on page 42) then

an OCP fault is declared and enters a fault state.

The fault state is latched if bit OCP_LAT in register Config49

is set high. The OCP fault state is not cleared until the power

to the IC is recycled. Otherwise, if bit OCP_LAT is set low, the

system is restarted after a specified amount of time configured

by using the bit FAULT_SLOW and bits RESTART[5:0] in

83" on page 43). The fault behavior during the fault state

initiated by this protection depends on the setting for bit

FAULT_SHDN in register Config51.

5.8.8 Open Loop Protection

Open loop protection (OLP) and sense resistor short

protection are implemented by monitoring the voltage across

the sense resistor. Open loop protection is enabled by setting

bit OLP to ‘0’ in register Config47 (see "Configuration 47

(Config47) – Address 79" on page 41). If the voltage on pin

FBSENSE does not reach the protection threshold (VOLP(th))

of 200mV during a 250ns scan period after the second stage

gate drive is turned ‘ON’ and the blanking window configured

by bits OLP_BLANK[2:0] in register Config48 (see

"Configuration 48 (Config48) – Address 80" on page 42) has

elapsed, then the OLP event accumulator is incremented by 1.

If the OLP comparator threshold is exceeded during this time,

the event accumulator is decremented by 1. If the event

accumulator count exceeds or equals the count set by bits

OLP_CNT[2:0] in register Config49 (see "Configuration 49

(Config49) – Address 81" on page 42) then an OLP fault is

declared and enters a fault state.

The fault state is latched if bit OCP_LAT in register Config49

is set high. The OLP fault state is not cleared until the power

to the IC is recycled. Otherwise, if bit OLP_LAT is set low, the

system is restarted after a specified amount of time configured

by using the bit FAULT_SLOW and bits RESTART[5:0] in

83" on page 43). The fault behavior during the fault state

initiated by this protection depends on the setting for bit

FAULT_SHDN in register Config51.

5.9 Overtemperature Protection

The CS1630/31 incorporates an internal overtemperature

protection (iOTP) circuit for IC protection and the circuitry

required to connect an external overtemperature protection

(eOTP) device. Typically, an NTC thermistor is used.

5.9.1 Internal Overtemperature Protection

Internal overtemperature protection (iOTP) is activated and

power switching devices are disabled when the die

temperature of the CS1630/31 exceeds 135°C. A hysteresis

of about 7°C occurs before resuming normal operation.

5.9.2 External Overtemperature Protection

The external overtemperature protection (eOTP) pin is used to

implement overtemperature protection using an external

negative temperature coefficient (NTC) thermistor, RNTC. The

total resistance on the eOTP pin is converted to an 8-bit digital

‘CODE’ (which gives an indication of the temperature) using a

digital feedback loop that adjusts the current (ICONNECT) into

the NTC and series resistor, RS, to maintain a constant

reference voltage of 1.25V (VCONNECT(th)). Figure 21

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