DC SPECIFICATIONS

Test

AD6640AST

Parameter

Temp

Level

Min

Typ

Max

Units

RESOLUTION

12

Bits

ACCURACY

No Missing Codes

+25

°C

I

GUARANTEED

Offset Error

Full

VI

–10

3.5

+10

mV

Gain Error

Full

VI

–10

4.0

+10

% FS

Differential Nonlinearity (DNL)

1

+25

°C

I

–1.0

±0.5

+1.5

LSB

Integral Nonlinearity (INL)

1

Full

V

±1.25

LSB

TEMPERATURE DRIFT

Offset Error

Full

V

50

ppm/

°C

Gain Error

Full

V

100

ppm/

°C

POWER SUPPLY REJECTION (PSRR)

Full

V

±0.5

mV/V

2

Full

V

2.4

V

ANALOG INPUTS (AIN,

Analog Input Common-Mode Range

4

Full

V

V

Differential Input Voltage Range

Full

V

2.0

V p-p

Differential Input Resistance

Full

IV

0.7

0.9

1.1

k

Ω

Differential Input Capacitance

+25

°C

V

1.5

pF

POWER SUPPLY

Supply Voltage

Full

VI

4.75

5.0

5.25

V

Full

VI

3.0

3.3

5.25

V

Supply Current

Full

VI

135

160

mA

Full

VI

10

20

mA

POWER CONSUMPTION

Full

VI

710

865

mW

NOTES

AIN should be driven at levels V

produce a 2 V p-p differential input signal. See Driving the Analog Inputs section for more details.

Specifications subject to change without notice

.

DIGITAL SPECIFICATIONS

Test

AD6640AST

Parameter

Temp

Level

Min

Typ

Max

Units

LOGIC INPUTS (ENC,

Encode Input Common-Mode Range

2

Full

IV

0.2

2.2

V

Differential Input Voltage

Full

IV

0.4

V p-p

Single-Ended Encode

10

V p-p

TTL/CMOS

Logic “1” Voltage

Full

VI

2.0

5.0

V

Logic “0” Voltage

Full

VI

0

0.8

V

Full

VI

500

650

800

µA

Full

VI

–400

–320

–200

µA

Input Capacitance

+25

°C

V

2.5

pF

LOGIC OUTPUTS (

Logic Compatibility

CMOS

Full

VI

2.8

V

Full

VI

0.2

0.5

V

Full

IV

4.5

V

Full

IV

0.35

0.5

V

Output Coding

Twos Complement

NOTES

ENC differentially. See Encoding the AD6640 section for more details. Performance versus ENC/ENC power is

shown in Figure 18 under Typical Performance Characteristics.

differential input voltage of 0.4 V p-p. For differential input voltage swings greater than 0.4 V p-p, the common-mode range will change. The minimum value insures that the

for a differential input swing of 0.8 V, the min and max common-mode specs become 0.4 V and 2.4 V respectively).

ENC may be driven alone if desired, but performance will likely be degraded. Logic Compatibility specifications are provided to show that TTL or CMOS clock sources

will work. When driving only one encode input, bypass the complementary input to GND with 0.01

µF.

Specifications subject to change without notice.

REV. 0

–2–

AD6640–SPECIFICATIONS