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AD73322LAST 数据表(PDF) 6 Page - Analog Devices

部件名 AD73322LAST
功能描述  Low Cost, Low Power CMOS General-Purpose Dual Analog Front End
PDF  40 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD73322LAST 数据表(HTML) 6 Page - Analog Devices

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REV. 0
AD73322L
–6–
t3
t2
t1
Figure 1. MCLK Timing
t11
t7
t9
t10
t12
t7
t8
t8
SE (I)
SCLK (O)
SDIFS (I)
SDI (I)
SDOFS (O)
SDO (O)
THREE-
STATE
THREE-
STATE
THREE-
STATE
D15
D2
D1
D0
D14
D15
D0
D1
D14
D15
D15
Figure 4. Serial Port (SPORT)
t3
t1
t2
t13
* SCLK IS INDIVIDUALLY PROGRAMMABLE
IN FREQUENCY (MCLK/4 SHOWN HERE).
t4
t5
t6
MCLK
SCLK*
Figure 3. SCLK Timing
TO OUTPUT
PIN
2.1V
100 A
100 A
IOL
IOH
CL
15pF
Figure 2. Load Circuit for Timing Specifications



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