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AD73460 数据表(PDF) 1 Page - Analog Devices |
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AD73460 数据表(HTML) 1 Page - Analog Devices |
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1 / 32 page  REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD73460 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 Six-Input Channel Analog Front End FEATURES AFE PERFORMANCE Six 16-Bit A/D Converters Programmable Input Sample Rate Simultaneous Sampling 72 dB SNR 64 kS/s Maximum Sample Rate –80 dB Crosstalk Low Group Delay (25 s Typ per ADC Channel) Programmable Input Gain Single Supply Operation On-Chip Reference DSP PERFORMANCE 19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 400 Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode FUNCTIONAL BLOCK DIAGRAM SERIAL PORT SPORT 2 REF ADC3 ANALOG FRONT END SECTION ADC1 ADC2 ADC4 ADC5 ADC6 EXTERNAL ADDRESS BUS SERIAL PORTS SPORT 0 SHIFTER MAC ALU ARITHMETIC UNITS MEMORY PROGRAMMABLE I/O AND FLAGS BYTE DMA CONTROLLER TIMER ADSP-2100 BASE ARCHITECTURE POWER-DOWN CONTROL PROGRAM SEQUENCER DAG 2 DATA ADDRESS GENERATORS PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA DAG 1 16K DM (OPTIONAL 8K) 16K PM (OPTIONAL 8K) EXTERNAL DATA BUS FULL MEMORY MODE SPORT 1 AD73460 GENERAL DESCRIPTION The AD73460 is a six-input channel analog front-end processor for general-purpose applications including industrial power meter- ing or multichannel analog inputs. It features six 16-bit A/D conversion channels, each of which provides 72 dB signal-to-noise ratio over a dc-to-2 kHz signal bandwidth. Each channel also features a programmable input gain amplifier (PGA) with gain settings in eight stages from 0 dB to 38 dB. The AD73460 is particularly suitable for industrial power metering as each channel samples synchronously, ensuring that there is no (phase) delay between the conversions. The AD73460 also features low group delay conversions on all channels. An on-chip reference voltage of 1.25 V is included. The sampling rate of the device is programmable with separate settings offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz sampling rates (from a master clock of 16.384 MHz), while the serial port (SPORT2) allows easy expansion of the number of input channels by cas- cading an extra AFE external to the AD73460. The AD73460’s DSP engine combines the ADSP-2100 family base architecture (three computational units, data address gen- erators, and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory. The AD73460-80 integrates 80K bytes of on-chip memory configured as 16K words (24-bit) of program RAM and 16K (16-bit) of data RAM. The AD73460-40 integrates 40K bytes of on-chip memory configured as 8K words (24-bit) of program RAM and 8K (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery-operated portable equipment. The AD73460 is available in a 119-ball PBGA package. |
类似零件编号 - AD73460 |
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类似说明 - AD73460 |
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