SSL4120 datasheet(8/48 Pages) NXP

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SSL4120

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Product data sheet

Rev. 2 — 1 November 2012

8 of 48

NXP Semiconductors

SSL4120

Resonant power supply controller IC with PFC for LED lighting

• Boost charge state

The PFC controller is switching; the HBC controller is off. The current from the

high-voltage start-up source is large enough to supply the SUPIC pin (current

consumption < Ich(nom)(SUPIC)).

• Operational supply state

Both the PFC and HBC controllers are switching. Current consumption is Ioper(SUPIC).

When the HBC controller is enabled, the switching frequency is initially high and the

HBC MOSFET drivers current consumption is dominant. The stored energy in CSUPIC

supplies the initial SUPIC current before the SUPIC supply source takes over.

The SUPIC pin has a low short-circuit detection voltage (Vscp(SUPIC) =0.65V). The current

dissipated in the HV start-up source is limited while VSUPIC < Vscp(SUPIC) (see

Section 7.2.4).

7.2.2 Regulated supply (SUPREG pin)

The voltage range on the SUPIC pin exceeds that of the external MOSFETs gate

voltages. The SSL4120 contains an integrated series stabilizer for this reason. The series

stabilizer creates an accurate regulated voltage (Vreg(SUPREG) = 10.9 V) at the buffer

capacitor CSUPREG. This stabilized voltage is used to:

• supply the internal PFC driver

Remark: The internal SUPIC pin supply provides most of the external MOSFET charge

current.

• supply the internal low-side HBC driver

• supply the internal high-side driver using external components

• as a reference voltage for optional external circuits

The SUPREG series stabilizer is enabled after CSUPIC has been fully charged. Enabling

the stabilizer after charging CSUPIC ensures any optional external circuitry connected to

SUPREG does not dissipate any of the start-up current.

To ensure that the external MOSFETs receive sufficient gate drive current, the voltage on

the SUPREG pin must reach Vstart(SUPREG). In addition, the voltage on the SUPIC pin must

reach the start level. The IC starts operating when both voltages reach their start levels.

SUPREG is provided with undervoltage protection (UVP-SUPREG; see Section 7.9).

When VSUPREG <Vuvp(SUPREG) = 10.3 V, two events are triggered:

• The IC stops operating to prevent unreliable switching because the gate driver voltage

is too low. The PFC controller stops switching immediately but the HBC controller

continues until the low-side stroke is active.

• The maximum current from the internal SUPREG series stabilizer is reduced to

Ich(red)(SUPREG) = 5.4 mA. This feature reduces the dissipation in the series stabilizer

when an overload occurs at the SUPREG pin while the SUPIC pin is supplied from an

external DC supply.

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