REV. G

–12–

AD7416/AD7417/AD7418

or the addresses can be set to avoid conflicts with other devices

on the bus. The four MSBs of this address for the AD7418 are set

to 0101, while the three LSBs are all set to zero.

If a serial communication occurs during a conversion operation,

the conversion will stop and will restart after the communication.

The serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a start

condition, defined as a high-to-low transition on the serial

data line, SDA, while the serial clock line, SCL, remains

high. This indicates that an address/data stream will follow.

All slave peripherals connected to the serial bus respond to

the 7-bit address (MSB first) plus an R/

W bit, which deter-

mines the direction of the data transfer, i.e., whether data

will be written to or read from the slave device.

The peripheral whose address corresponds to the transmitted

address responds by pulling the data line low during the low

period before the ninth clock pulse, known as the Acknowl-

edge bit. All other devices on the bus now remain idle while

the selected device waits for data to be read from or written

to it. If the R/

W bit is a 0, then the master will write to the

slave device. If the R/

W bit is a 1, then the master will read

from the slave device.

2. Data is sent over the serial bus in sequences of nine clock

pulses, eight bits of data followed by an Acknowledge bit

from the receiver of data. Transitions on the data line must

occur during the low period of the clock signal and remain

stable during the high period, since a low-to-high transition

when the clock is high may be interpreted as a stop signal.

3. When all data bytes have been read or written, stop condi-

tions are established. In write mode, the master will pull the

data line high during the 10th clock pulse to assert a stop

condition. In read mode, the master device will pull the data

line high during the low period before the 9th clock pulse.

This is known as No Acknowledge. The master will then take

the data line low during the low period before the 10th clock

pulse, then high during the 10th clock pulse to assert a stop

condition.

Any number of bytes of data may be transferred over the serial

bus in one operation, but it is not possible to mix read and write

in one operation because the type of operation is determined at

the beginning and cannot subsequently be changed without

starting a new operation.

WRITING TO THE AD7416/AD7417/AD7418

Depending on the register being written to, there are three

different writes for the AD7416/AD7417/AD7418.

1. Writing to the Address Pointer Register for a subsequent read.

In order to read data from a particular register, the Address

Pointer Register must contain the address of that register. If

it does not, the correct address must be written to the Address

Pointer Register by performing a single-byte write operation,

as shown in Figure 8. The write operation consists of the

serial bus address followed by the address pointer byte. No

data is written to any of the data registers.

2. Writing a single byte of data to the configuration registers or

The Configuration Register is an 8-bit register, so only one

byte of data can be written to it. If only 8-bit temperature

comparisons are required, the temperature LSB can be

Writing a single byte of data to one of these registers consists

of the serial bus address, the data register address written to

R/

W

1

SCL

SDA

00

1

A2

A1

A0

P7

P6

P5

P4

P3

P2

P1

P0

ACK. BY

AD7416

STOP BY

MASTER

START BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

19

1

ACK. BY

AD7416

9

Figure 8. Writing to the Address Pointer Register to Select a Data Register for a Subsequent Read Operation

R/

W

1

SCL

SDA

00

1

A2

A1

A0

P7

P6

P5

P4

P3

P2

P1

P0

ACK. BY

AD7416

START BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

19

1

ACK. BY

AD7416

9

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY

AD7416

STOP BY

MASTER

FRAME 3

DATA BYTE

19

SCL (CONTINUED)

SDA (CONTINUED)

Figure 9. Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Data Register