REV. D

–12–

AD7476/AD7477/AD7478

INPUT FREQUENCY – Hz

–50

10k

–55

–60

–65

–70

–75

100k

1M

–80

–85

–90

INPUT FREQUENCY – Hz

–72

10k

–74

–76

–78

–80

100k

1M

–82

–84

Digital Inputs

The digital inputs applied to the AD7476/AD7477/AD7478 are

not limited by the maximum ratings that limit the analog inputs.

Instead, the digital inputs applied can go to 7 V and are not

example, if the AD7476/AD7477/AD7478 were operated with a

inputs. However, it is important to note that the data output on

advantage of SCLK and

CS not being restricted by the V

0.3 V limit is the fact that power supply sequencing issues are

avoided. If

CS or SCLK is applied before V

latch-up as there would be on the analog inputs if a signal greater

MODES OF OPERATION

The mode of operation of the AD7476/AD7477/AD7478 is

selected by controlling the (logic) state of the

CS signal during a

conversion. There are two possible modes of operation, Normal

mode and Power-Down mode. The point at which

CS is pulled

high after the conversion has been initiated will determine whether

or not the AD7476/AD7477/AD7478 will enter Power-Down

mode. Similarly, if already in power-down,

CS can control

whether the device will return to normal operation or remain in

power-down. These modes of operation are designed to provide

flexible power management options. These options can be chosen

to optimize the power dissipation/throughput rate ratio for different

application requirements.

Normal Mode

This mode is intended for fastest throughput rate performance,

as the user does not have to worry about any power-up times

with the AD7476/AD7477/AD7478 remaining fully powered all

the time. Figure 11 shows the general diagram of the operation

of the AD7476/AD7477/AD7478 in this mode.

The conversion is initiated on the falling edge of

CS as described

in the Serial Interface section. To ensure the part remains fully

powered up at all times,

CS must remain low until at least 10

SCLK falling edges have elapsed after the falling edge of

CS. If

CS is brought high any time after the tenth SCLK falling edge,

but before the sixteenth SCLK falling edge, the part will remain

powered up but the conversion will be terminated and SDATA

will go back into three-state. Sixteen serial clock cycles are

required to complete the conversion and access the complete

4 LEADING ZEROS + CONVERSION RESULT

CS

SCLK

SDATA

1

10

16

Figure 11. Normal Mode Operation

1

10

16

2

THREE-STATE

CS

SCLK

SDATA

Figure 12. Entering Power-Down Mode