PCA9554B_PCA9554C

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Product data sheet

Rev. 1 — 19 September 2012

7 of 36

NXP Semiconductors

PCA9554B; PCA9554C

6.4.4 Configuration register (03h)

The Configuration register (register 3) configures the direction of the I/O pins. If a bit in this

register is set to 1, the corresponding port pin is enabled as a high-impedance input. If a

bit in this register is cleared to 0, the corresponding port pin is enabled as an output.

6.5 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the

Output port register. In this case, there are low-impedance paths between the I/O pin and

recommended levels for proper operation.

Table 9.

Configuration register (address 03h)

Bit

7

6

5

4

3

2

1

0

Symbol

C7

C6

C5

C4

C3

C2

C1

C0

Default

11

11

11

11

On power-up or reset, all registers return to default values.

Fig 6.

Simplified schematic of the I/Os (P0 to P7)

P0 to P7

output port

register data

configuration

register

DQ

CK

Q

data from

shift register

write configuration

pulse

output port

register

DQ

CK

write pulse

polarity inversion

register

DQ

CK

data from

shift register

write polarity

pulse

input port

register

DQ

CK

read pulse

input port

register data

polarity inversion

register data

002aah123

FF

data from

shift register

FF

FF

FF

Q1

Q2

to INT

100 kΩ