REV. PrA

PRELIMINARY TECHNICAL DATA

AD7667

–21–

IRQ

MC68HC11*

CNVST

AD7667*

CS

BUSY

MISO/SDI

SCK

I/O PORT

SDOUT

SCLK

RD

INVSCLK

EXT/INT

SER/PAR

DVDD

*

ADDITIONAL PINS OMITTED FOR CLARITY

DVDD

Figure 21. Interfacing the AD7667 to SPI Interface

ADSP-21065L in Master Serial Interface

As shown in Figure 22, the AD7667 can be interfaced to

the ADSP-21065L using the serial interface in master mode

without any glue logic required. This mode combines the

advantages of reducing the number of wire connections and

being able to read the data during or after conversion at user

convenience.

The AD7667 is configured for the internal clock mode (EXT/

INT low) and acts, therefore, as the master device. The con-

vert command can be generated by either an external low

jitter oscillator or, as shown, by a FLAG output of the ADSP-

21065L or by a frame output TFS of one serial port of the

ADSP-21065L which can be used as a timer. The serial port

on the ADSP-21065L is configured for external clock (IRFS

= 0), rising edge active (CKRE = 1), external late framed

sync signals (IRFS = 0, LAFS = 1, RFSR = 1) and active

high (LRFS = 0). The serial port of the ADSP-21065L is

configured by writing to its receive control register

(SRCTL)—see ADSP-2106x SHARC User’s Manual. Be-

cause the serial port within the ADSP-21065L will be seeing a

discontinuous clock, an initial word reading has to be done after

the ADSP-21065L has been reset to ensure that the serial

port is properly synchronized to this clock during each follow-

ing data read operation.

RFS

ADSP-21065L*

SHARC

CNVST

AD7667*

CS

SYNC

RD

DR

RCLK

FLAG OR TFS

SDOUT

SCLK

INVSYNC

INVSCLK

EXT/INT

RDC/SDIN

SER/PAR

DVDD

DVDD

Figure 22. Interfacing to the ADSP-21065L Using the

Serial Master Mode

APPLICATION HINTS

Bipolar and Wider Input Ranges

In some applications, it is desired to use a bipolar or wider

analog input range like, for instance, ±10 V, ±5 V or 0 V to 5 V.

Although the AD7667 has only one unipolar range, by simple

modifications of the input driver circuitry, bipolar and wider

input ranges can be used without any performance degradation.

Figure 23 shows a connection diagram which allows

that. Components values required and resulting full-

scale ranges are shown in Table II.

For applications where accurate gain and offset are de-

sired, they can be calibrated by acquiring a ground and a

voltage reference using an analog multiplexer, U2, as

shown for bipolar input ranges in Figure 23.

U1

ANALOG

INPUT

R2

R3

R4

100nF

R1

U2

IN

INGND

REF

REFGND

100nF

AD7667

Figure 23. Using the AD7667 in 16-Bit Bipolar and/or

Wider Input Ranges

Table II. Component Values and Input Ranges

Input Range

R1

R2

R3

R4

±10 V

250

2 k

10 k

8 k

±5 V

500

2 k

10 k

6.67 k

0 V to –5 V

1 k

2 k

None

0

Layout

The AD7667 has very good immunity to noise on the

power supplies as can be seen in Figure 9. However, care

should still be taken with regard to grounding layout.

The printed circuit board that houses the AD7667 should be

designed so the analog and digital sections are separated and

confined to certain areas of the board. This facilitates the use

of ground planes that can be easily separated. Digital and

analog ground planes should be joined in only one place,

preferably underneath the AD7667, or, at least, as close as

possible to the AD7667. If the AD7667 is in a system where

multiple devices require analog-to-digital ground connections,

the connection should still be made at one point only, a star

ground point, which should be established as close as possible

to the AD7667.

It is recommended to avoid running digital lines under

the device as these will couple noise onto the die. The ana-

log ground plane should be allowed to run under the

AD7667 to avoid noise coupling. Fast switching signals

like

CNVST or clocks should be shielded with digital

ground to avoid radiating noise to other sections of the

board, and should never run near analog signal paths.

Crossover of digital and analog signals should be avoided.

Traces on different but close layers of the board should run