AD7721

REV. A

–4–

Parameter

(A, S Versions)

Units

Conditions/Comments

Serial Interface

3

100

kHz min

Master Clock Frequency

15

MHz max

15 MHz for Specified Performance

0.45

× t

CLK

ns min

Master Clock Input Low Time

0.45

× t

CLK

ns min

Master Clock Input High Time

ns nom

DRDY High Time

4

ns min

RFS Low to SCLK Falling Edge Setup Time

20

ns max

RFS Low to Data Valid Delay

ns nom

SCLK High Pulse Width

ns nom

SCLK Low Pulse Width

25

ns max

SCLK Rising Edge to Data Valid Delay

0

ns min

RFS to SCLK Falling Edge Hold Time

5

0

ns min

Bus Relinquish Time after Rising Edge of

RFS

20

ns max

32

× t

CLK

ns nom

Period between Consecutive

DRDY Rising Edges

Parallel Interface

3

100

kHz min

Master Clock Frequency

10

MHz max

10 MHz for Specified Performance

0.45

× t

CLK

ns min

Master Clock Input Low Time

0.45

× t

CLK

ns min

Master Clock Input High Time

Read Operation

2

× t

CLK

ns nom

DRDY High Time

30

ns max

Data Access Time after Falling Edge of

DRDY

32

× t

CLK

ns nom

Period between Consecutive

DRDY Rising Edges

Write Operation

35

ns min

WR Pulse Width

20

ns min

Data Valid to

WR High Setup Time

0

ns min

Data Valid to

WR High Hold Time

NOTES

The timing is measured with a load of 50 pF on SCLK and

DRDY. SCLK can be operated with a load capacitance of 50 pF maximum.

°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

ization to operate with CLK frequencies down to 100 kHz.

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics is the true bus

relinquish time of the part and, as such, is independent of external bus loading capacitance.

TO

OUTPUT

PIN

+1.6V

50pF

1.6mA

200 A

Figure 1. Load Circuit for Access Time and Bus Relinquish Time

5%; AGND = DGND = 0 V, REFIN = +2.5 V

unless otherwise noted)