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AD7769AP 数据表(PDF) 4 Page - Analog Devices |
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AD7769AP 数据表(HTML) 4 Page - Analog Devices |
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4 / 16 page  AD7769 –4– REV. A TIMING CHARACTERISTICS1, 2 (VCC = +5 V 5%; VDD = +12 V 10%; AGND [ADC] = AGND [DAC] = DGND = 0 V. For ADC and DAC, VBIAS = +5 V, VSWING = +2.5 V.) Limit at Limit at Parameter Label +25 CTMIN, TMAX Units Test Conditions/Comments ADC /DAC CONTROL TIMING CS to WR Setup Time t1 0 0 ns min CS to WR Hold Time t2 0 0 ns min ADC/DAC to WR Setup Time t3 00 ns ADC/DAC to WR Hold Time t4 0 0 ns min CHA/CHB to WR Setup Time t5 0 0 ns min CHA/CHB to WR Hold Time t6 0 0 ns min WR Pulse Width t7 80 80 ns min ADC CONVERSION TIMING Using External Clock Load Circuit of Figure 3, CL = 20 pF WR to INT Low Delay t8 2.6 2.6 µs max Using Internal Clock Load Circuit of Figure 3, CL = 20 pF WR to INT Low Delay t8 1.9/3.0 1.9/3.0 µs min/max Typically 2.5 µs WR to INT High Delay t9 85 85 ns max Load Circuit of Figure 3, CL = 20 pF t9 120 120 ns max Load Circuit of Figure 3, CL = 100 pF WR to Data Valid Delay 3 t10 t8+70 t8+70 ns max Load Circuit of Figure 1, CL = 20 pF t10 t8+110 t8+110 ns max Load Circuit of Figure 1, CL = 100 pF ADC READ TIMING CS to RD Setup Time t11 0 0 ns min CS to RD Hold Mode t12 0 0 ns min RD to Data Valid Delay3 t13 15/65 15/65 ns min/max Load Circuit of Figure 1, CL = 20 pF t13 30/100 30/100 ns min/max Load Circuit of Figure 1, CL = 100 pF Bus Relinquish Time after RD High 4 t14 15/65 15/65 ns min/max Load Circuit of Figure 2 RD to INT High Delay t15 80 80 ns max Load Circuit of Figure 3, CL = 20 pF t15 110 110 ns max Load Circuit of Figure 3, CL = 100 pF RD Pulse Width t16 t13 t13 ns min Determined by t13 DAC WRITE TIMING Data Valid to WR Setup Time t17 65 65 ns nıin Data Valid to WR Hold Time t18 15 20 ns min WR to DAC Output Settling Time t19 44 µs max Load Circuit of Figure 4 NOTES 1See Figures 11, 12 and 13. 2Sample tested at +25 °C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 3t 10 and t13 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 4t 14 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2. Specifications subject to change without notice. Figure 4. Load Circuit for DAC Settling Time Test Figure 1. Load Circuits for Data Access Time Test Figure 2. Load Circuits for Bus Relinquish Time Test Figure 3. Load Circuit for RD and WR to INT Delay Test |
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